AM79C940JCSLASHW datasheet(65/144 Pages) AMD

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Am79C940

Transmit Start Point

Bit 3-1

RES

Reserved. Read as zeroes. Al-

ways write as zeroes.

Bit 0

SWRST

Software Reset. When set, pro-

vides an equivalent of the hard-

ware RESET pin function. All

default values. The MACE de-

vice will require re-initialization

after SWRST has been activat-

ed. The MACE device will clear

SWRST during its internal reset

sequence.

FIFO Configuration Control

(REG ADDR 12)

(FIFOCC)

All bits within the FIFO Configuration Control register

will be set to their default state upon a hardware or soft-

ware reset. Bit assignments are as follows:

Bit

Name

Description

Bit 7-6

XMTFW

Transmit

FIFO

Watermark.

[1-0]

XMTFW

controls

the

point

TDTREQ is asserted in relation

to the number of write cycles to

the Transmit FIFO. TDTREQ will

be asserted at any time that the

number of write cycles specified

by XMTFW can be executed.

XMTFW is set to a value of 00 (8

cycles)

after

hardware

software reset.

Transmit FIFO Watermarks

The XMTFW value will only be

updated when the XMTFWU bit

is set.

To ensure that sufficient space

is present in the XMTFIFO to

accept the specified number of

write

cycles

(including

End-Of-Frame

delimiter),

TDTREQ may go inactive before

the XMTSP threshold is reached

when using the non burst mode

(XMTBRST = 0). The host must

be aware that despite TDTREQ

going inactive, additional space

exists in the XMTFIFO, and the

data write must continue to

ensure the XMTSP threshold is

achieved. No transmit activity

will commence until the XMTSP

threshold

reached.

When

using the burst mode, TDTREQ

will not be de-asserted until only

a single write cycle can be per-

formed. See the FIFO Sub-sys-

tem section for additional de-

tails.

Bit 5-4

RCVFW

Receive

FIFO

Watermark.

[1-0]

RCVFW

controls

the

point

RDTREQ is asserted in relation

to the number of bytes available

in the RCVFIFO. RCVFW speci-

fies the number of bytes which

must be present (once the pack-

has

been

verified

non-runt), before the RDTREQ

is asserted. Note however that in

order for RDTREQ to be activat-

ed for a new frame, at least

64-bytes

must

have

been

received. This effectively avoids

reacting to receive frames which

are runts or suffer a collision dur-

ing the slot time (512 bit times).

If the Runt Packet Accept fea-

ture (RPA in Receive Frame

Control)

enabled,

the

RDTREQ pin will be activated as

soon as either 64-bytes are

received, or a complete valid

receive

frame

detected

(regardless of length). RCVFW

is set to a value of 10 (64 bytes)

after hardware or software reset.

Receive FIFO Watermarks

The RCVFW value will only be

updated when the RCVFWU bit

is set.

Bit 3

XMTFWU

Transmit

FIFO

Watermark

Update. Allows update of the

XMTSP [1-0]

Bytes

112

XMTFW[1-0]

RCVFW [1-0]

XMTFWU

RCVFWU

XMTBRST

RCVBRST

XMTSP [1–0]

Bytes

XMTSP [1–0]

Bytes

AM79C940JC/W Datasheet(PDF) 65 Page - Advanced Micro Devices

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