AM79C940JCSLASHW datasheet(71/144 Pages) AMD

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Physical Address

(PADR [47-00])

(REG ADDR 21

)

This 48-bit value represents the unique node value

assigned by the IEEE and used for internal address

comparison. After a hardware or software reset and

before the ENRCV bit in the MAC Configuration Con-

trol register has been set, the Physical Address can be

accessed by setting the PHYADDR bit in the Internal

Address Configuration register (REG ADDR 18) and

then by performing 6 reads or writes to the Physical

Address. Once ENRCV has been set, the ADDRCHG

bit in the Internal Address Configuration register must

be set and be polled until it is cleared by the MACE

device before setting the PHYADDR bit and before

accessing of the Physical Address is allowed. The first

bit of the incoming address must be a 0 for a physical

address. The incoming address is compared against

the value stored in the Physical Address register at ini-

tialization provided that the DRCVPA bit in the MAC

Configuration Control register is cleared.

Missed Packet Count (MPC)

(REG ADDR 24)

The Missed Packet Count (MPC) is a read only 8-bit

counter. The MPC is incremented when the receiver is

unable to respond to a packet which would have nor-

mally been passed to the host. The MPC will be reset

to zero when read. The MACE device will be deaf to

receive traffic due to any of the following conditions:

s The host disabled the receive function by clearing

the ENRCV bit in the MAC Configuration Control

s A Receive FIFO overflow condition exists, and must

be cleared by reading the Receive FIFO and the

Receive Frame Status.

s The Receive Frame Count (RCVFC) in the FIFO

Frame Count register exceeds its maximum value,

indicating that greater than 15 frames are in the

Receive FIFO.

If the number of received frames that have been

missed exceeds 255, the MPC will roll over and con-

tinue counting from zero, the MPCO (Missed Packet

Count Overflow) bit in the Interrupt Register will be set

(at the value 255), and the INTR pin will be asserted

providing that MPCOM (Missed Packet Count Overflow

Mask) in the Interrupt Mask Register is clear. MPCOM

will be cleared (the interrupt will be unmasked) after a

hardware or software reset.

Note that the following conditions apply to the MPC:

s After hardware or software reset, the MPC will not

increment until the first time the receiver is enabled

(ENRCV = 1). Once the receiver has been enabled,

the MPC will count all missed packet events,

regardless of the programming of ENRCV.

s The packet must pass the internal address match to

be counted. Any of the following address match

conditions will increment MPC while the receiver is

deaf:

Physical Address match;

Logical Address match;

Broadcast reception;

Any receive in promiscuous mode (PROM = 1 in the

MAC Configuration Control register);

EADI feature match mode and EAM is asserted;

EADI feature reject mode and EAR is not asserted.

s Any packet which suffers a collision within the slot

time will not be counted.

s Runt packets will not be counted unless RPA in the

User Test Register is enabled.

s Packets which pass the address match criteria but

experience FCS or Framing errors will be counted,

since they are normally passed to the host.

Runt Packet Count (RNTPC)

(REG ADDR 26)

The Runt Packet Count (RNTPC) is a read only 8-bit

counter, incremented when the receiver detects a runt

packet that is addressed to this node. Runt packets are

defined as received frames which passed the internal

address match criteria but did not contain a minimum

of 64-bytes of data after SFD. Note that the RNTPC

value returned in the Receive Frame Status (RFS2) will

freeze at a value of 255, whereas this register based

version of RNTPC is free running. The value will roll

over after 255 runt packets have been detected, setting

the RNTPCO bit (in the Interrupt Register and assert-

ing the INTR pin if the corresponding mask bit (RNTP-

COM in the Interrupt Mask Register) is cleared.

RNTPC will be reset to zero when read.

Receive Collision Count (RCVCC)(REG ADDR 27)

The Receive Collision Count (RCVCC) is a read only

8-bit counter, incremented when the receiver detects a

collision on the network. Note that the RCVCC value

returned in the Receive Frame Status (RFS3) will

freeze at a value of 255, whereas this register based

version of RCVCC is free running. The value will roll

over after 255 receive collisions have been detected,

setting the RCVCCO bit (in the Interrupt Register and

asserting the INTR pin if the corresponding mask bit

(RCVCCOM in the Interrupt Mask Register) is cleared.

RCVCC will be reset to zero when read.

User Test Register (UTR)

(REG ADDR 29)

The User Test Register is used to put the chip into test

configurations. All bits within the Test Register are

cleared upon a hardware or software reset. Bit

assignments are as follows:

PADR [47–00]

MPC [7–0]

RTRE

RTRD

RPA

FCOLL

RCVFCSE

LOOP [1-0]

FD_TEST

RNTPC [7–0]

RCVCC [7–0]

AM79C940JC/W Datasheet(PDF) 71 Page - Advanced Micro Devices

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