AM79C940JCSLASHW datasheet(31/144 Pages) AMD

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Am79C940

Transmit FIFO will not return DTV if ENXMT is dis-

abled, and no data will be written. The MACE device

will commence the preamble sequence once the

Transmit Start Point (XMTSP bits in BIU Configuration

Control register) threshold is reached in the Transmit

FIFO.

The Transmit FIFO data will not be overwritten until at

least 512 data bits have been transmitted onto the net-

work. If a collision occurs within the slot time (512 bit

time) window, the MACE device will generate a jam se-

quence (a 32-bit all zeroes pattern) before ceasing the

transmission. The Transmit FIFO will be reset to point

at the start of the transmit data field, and the message

will be retried after the random back-off interval has

expired.

DETAILED FUNCTIONS

Block Level Description

The following sections describe the major sub-blocks

of and the external interfaces to the MACE device.

Bus Interface Unit (BIU)

The BIU performs the interface between the host or

system bus and the Transmit and Receive FIFOs, as

well as all chip control and status registers. The BIU

can be configured to accept data presented in either lit-

tle-endian or big indian format, minimizing the external

logic required to access the MACE device internal

FIFOs and registers. In addition, the BIU directly

supports 8-bit transfers and incorporates features to

simplif y int e r f acing to 32- bit sy st ems using

external latches.

Externally, the FIFOs appear as two independent reg-

isters located at individual addresses. The remainder

of the internal registers occupy 30 additional consecu-

tive addresses, and appear as 8-bits wide.

BIU to FIFO Data Path

The BIU operates assuming that the 16-bit data path

to/from the internal FIFOs is configured as two inde-

pendent byte paths, activated by the Byte Enable

sig nals BE0 and BE1.

BE0 and BE1 are only used during accesses to the

16-bit wide Transmit and Receive FIFOs. After hard-

ware or software reset, the BSWP bit will be cleared.

FIFO accesses to the MACE device will operate

assuming an Intel 80x86 type memory convention

(most significant byte of a word stored in the higher

addressed byte). Word data transfers to/from the

FIFOs over the DBUS15-0 lines will have the least sig-

nificant byte located on DBUS7-0 (activated by BE0)

and the most significant byte located on DBUS15-8

(activated by BE1).

FIFO data can be read or written using either byte and/

or word operations.

If byte operation is required, read/write transfers can be

performed on either the upper or lower data bus by

asserting the appropriate byte enable. For instance

with BSWP = 0, reading from or writing to DBUS15-8 is

accomplished by asserting BE1, and allows the data

stream to be read from or written to the appropriate

FIFO in byte order (byte 0, byte 1,....byte n). It is equally

valid to read or write the data stream using DBUS7–0

and by asserting BE0. For BSWP = 1, reading from or

writing to DBUS15-8 is accomplished by asserting BE0,

and allows the byte stream to be transferred in byte

order.

When word operations are required, BSWP ensures

that the byte ordering of the target memory is compati-

ble with the 802.3 requirement to send/receive the data

stream in byte ascending order. With BSWP = 0, the

data transferred to/from the FIFO assumes that byte n

will be on DBUS7-0 (activated by BE0) and byte n+1

will be on DBUS15-8 (activated by BE1). With BSWP =

1, the data transferred to/from the FIFO assumes that

byte n will be presented on DBUS15-8 (activated by

BE0), and byte n+1 will be on DBUS7-0 (activated by

BE1).

There are some additional special cases to the above

generalized rules, which are as follows:

(a) When performing byte read operations, both

halves of the data bus are driven with identical

data, effectively allowing the user to arbitrarily read

from either the upper or lower data bus, when only

one of the byte enables is activated.

(b) When byte write operations are performed, the

Transmit FIFO latency is affected. See the FIFO

Sub-System section for additional details.

a receive frame (EOF is asserted), and the mes-

sage contained an odd number of bytes but the

host requested a word operation by asserting both

BE0 and BE1, then the MACE device will present

one valid and one non-valid byte on the data bus.

The placement of valid data for the data byte is de-

pendent on the target memory architecture. Re-

gardless of BSWP, the single valid byte will be read

from the BE0 memory bank. If BSWP = 0, BE0 cor-

responds to DBUS7-0; if BSWP = 1, BE0 corre-

sponds to DBUS15-8.

(d) If a byte read is performed when the last data byte

is read for a receive frame (when the MACE device

activates the EOF signal), then the same byte will

be presented on both the upper and lower byte of

the data bus, regardless of which byte enable was

activated (as is the case for all byte read opera-

tions).

(e) When writing the last byte in a transmit message

to the Transmit FIFO, the portion of the data bus

AM79C940JC/W Datasheet(PDF) 31 Page - Advanced Micro Devices

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