PIC16CR74ESLASHSP datasheet(101/172 Pages) MICROCHIP

101 / 172 page

DS21993C-page 99

PIC16CR7X

12.11 Interrupts

The PIC16CR7X family has up to 12 sources of

interrupt. The Interrupt Control register (INTCON)

records individual interrupt requests in flag bits. It also

has individual and global interrupt enable bits.

A Global Interrupt Enable bit, GIE (INTCON<7>)

enables (if set) all unmasked interrupts, or disables (if

cleared) all interrupts. When bit GIE is enabled and an

interrupt’s flag bit and mask bit are set, the interrupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in

various registers. Individual interrupt bits are set,

regardless of the status of the GIE bit. The GIE bit is

cleared on Reset.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables interrupts.

The RB0/INT pin interrupt, the RB port change interrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

The peripheral interrupt flags are contained in the

Special Function Registers, PIR1 and PIR2. The corre-

sponding interrupt enable bits are contained in Special

Function Registers, PIE1 and PIE2, and the peripheral

interrupt enable bit is contained in Special Function

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs, relative to

the current Q cycle. The latency is the same for one or

two-cycle instructions. Individual interrupt flag bits are

set, regardless of the status of their corresponding

mask bit, PEIE bit or the GIE bit.

FIGURE 12-10:

INTERRUPT LOGIC

Note:

Individual interrupt flag bits are set,

regardless of the status of their corre-

sponding mask bit or the GIE bit.

PSPIF(1)

PSPIE(1)

ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

TMR0IF

TMR0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in Sleep mode)

Interrupt to CPU

CCP2IE

CCP2IF

Note 1:

PSP interrupt is implemented only on PIC16CR74/77 devices.

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