MPC8280 datasheet(1307/1386 Pages) FREESCALE

1307 / 1386 page

2C Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

40-5

3. After the first byte is shifted in, the slave compares the received data to its slave address. If the slave

is an MPC8280, the address is programmed in its I2C address register (I2ADD).

— If a match is found, the slave acknowledges the received byte and begins transmitting on the

clock pulse immediately following the acknowledge.

— If a match is found but the slave is not ready, the read request is not acknowledged and the

transaction is aborted. If the slave is an MPC8280, a maskable transmission error interrupt is

triggered to allow software to prepare data for transmission on the next try.

— If a mismatch occurs, the slave ignores the message and searches for a new start condition.

4. The master acknowledges each byte sent as long as an overrun does not occur. If the master

receiver fails to acknowledge a byte, the slave aborts transmission. For a slave MPC8280, the abort

generates a maskable interrupt. A maskable interrupt is also issued after a complete buffer is sent

or after an error. If an underrun occurs, the MPC8280 slave sends ones until a stop condition is

detected.

40.3.4

I2C Multi-Master Considerations

The I2C controller supports a multi-master configuration, in which the I2C controller must alternate

between master and slave modes. The I2C controller supports this by implementing I2C master arbitration

in hardware. However, due to the nature of the I2C bus and the implementation of the I2C controller, certain

software considerations must be made.

An MPC8280 I2C controller attempting a master read request could simultaneously be targeted for an

external master write (slave read). Both operations trigger the controller’s I2CER[RXB] event, but only

one operation wins the bus arbitration. To determine which operation caused the interrupt, software must

verify that its transmit operation actually completed before assuming that the received data is the result of

its read operation.

Problems could also arise if the MPC8280's I2C controller master sets up a transmit buffer and BD for a

write request, but then is the target of a read request from another master. Without software precautions,

the I2C controller responds to the other master with the transmit buffer originally intended for its own write

request. To avoid this situation, a higher-level handshake protocol must be used. For example, a master,

before reading a slave, writes the slave with a description of the requested data (which register should be

read, for example). This operation is typical with many I2C devices.

In addition, it is not recommended to enable the MPC8280’s I2C controller while another I2C master is

executing transactions on the bus. The MPC8280’s I2C controller should wait for the bus to become idle.

The MPC8280’s I2C controller assumes that other I2C devices on the bus closely conform to the I2C

specification. Unexpected behavior can occur if the MPC8280 I2C controller is connected with devices

which operate outside the specification. For example, a slave device which acknowledges a master write

with two SCL pulses instead of one (total of 10 SCL pulses), can cause wrong behavior of the

PowerQUICC I2C controller on its next transaction.

40.4

I2C Registers

The following sections describe the I2C registers.

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