MPC8280 datasheet(1310/1386 Pages) FREESCALE

1310 / 1386 page

2C Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

40-8

Freescale Semiconductor

the corresponding interrupt. Unmasked I2CER bits must be cleared before the CP clears internal interrupt

requests. Figure 40-9 shows both registers.

Table 40-4 describes the I2CER/I2CMR fields.

40.4.5

I2C Command Register (I2COM)

The I2C command register, shown in Figure 40-10, is used to start I2C transfers and to select master or

slave mode.

234567

Field

—

TXE

—

BSY

TXB

RXB

Reset

0000_0000

R/W

Addr

0x11870(I2CER)/0x11874 I2CMR)

Figure 40-9. I2C Event/Mask Registers (I2CER/I2CMR)

Table 40-4. I2CER/I2CMR Field Descriptions

Bits

Name

Description

0–2

—

Reserved and should be cleared.

TXE

Tx error. Set when an error occurs during transmission. This event is not maskable via the TxBD[I]

bit.

—

Reserved and should be cleared.

BSY

Busy. Set after the first character is received but discarded because no Rx buffer is available.

TXB

Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Two

character times must elapse to guarantee that all data has been sent.

RXB

Rx buffer. Set after the last character is written to the Rx buffer and the RxBD is closed.

01234567

Field

STR

—

M/S

Reset

0000_0000

R/W

Addr

0x1186C

Figure 40-10. I2C Command Register (I2COM)

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