MPC8280 datasheet(1308/1386 Pages) FREESCALE

1308 / 1386 page

2C Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

40-6

Freescale Semiconductor

40.4.1

I2C Mode Register (I2MOD)

The I2C mode register, shown in Figure 40-6, controls the I2C modes and clock source.

Table 40-1 describes I2MOD bit functions.

234

567

Field

—

REVD

GCD

FLT

PDIV

Reset

0000_0000

R/W

Addr

0x11860

Figure 40-6. I2C Mode Register (I2MOD)

Table 40-1. I

I2MOD Field Descriptions

Bits

Name

Description

0–1

—

Reserved and should be cleared.

REVD

Reverse data. Determines the Rx and Tx character bit order.

0 Normal operation. The msb (bit 0) of a character is transferred first.

1 Reverse data. the lsb (bit 7) of a character is transferred first.

Note: Clearing REVD is strongly recommended to ensure consistent bit ordering across devices.

GCD

General call disable. Determines whether the receiver acknowledges a general call address.

0 General call address is enabled.

1 General call address is disabled.

FLT

Clock filter. Determines if the I

2C input clock SCL is filtered to prevent spikes in a noisy environment.

0 SCL is not filtered.

1 SCL is filtered by a digital filter.

5–6

PDIV

Predivider. Selects the clock division factor before it is input into the I

2C BRG. The clock source for

the I2C BRG is the BRGCLK generated from the CPM clock; see Section 10.4, “System Clock

Control Register (SCCR).”

00 BRGCLK/32

01 BRGCLK/16

10 BRGCLK/8

11 BRGCLK/4

Note: To both save power and reduce noise susceptibility, select the PDIV with the largest division

factor (slowest clock) that still meets performance requirements.

Enable I2C operation.

2C is disabled. The I2C is in a reset state and consumes minimal power.

2C is enabled. Do not change other I2MOD bits when EN is set.

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