MPC8280 datasheet(1311/1386 Pages) FREESCALE

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2C Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

40-9

Table 40-5 describes I2COM fields.

40.5

I2C Parameter RAM

The I2C controller parameter table is used for the general I2C parameters and is similar to the SCC

general-purpose parameter RAM. The CP accesses the I2C parameter table using a user-programmed

pointer (I2C_BASE) located in the parameter RAM; see Section 14.5.2, “Parameter RAM.” The I2C

parameter table can be placed at any 64-byte aligned address in the dual-port RAM’s general-purpose area

(banks 1–8, 11 and 12). The user must initialize certain parameter RAM values before the I2C is enabled;

the CP initializes the other values. Software usually does not access parameter RAM entries once they are

initialized; they should be changed only when the I2C is inactive.

Table 40-6 shows the I2C parameter memory map.

Table 40-5. I2COM Field Descriptions

Bits

Name

Description

STR

Start transmit. In master mode, setting STR causes the I

2C controller to start sending data from the

2C Tx buffers if they are ready. In slave mode, setting STR when the I2C controller is idle causes it

to load the Tx data register from the I

2C Tx buffer and start sending when it receives an address

byte that matches the slave address with R/W = 1. STR is always read as a 0.

1–6

—

Reserved and should be cleared.

M/S

Master/slave. Configures the I2C controller to operate as a master or a slave.

0I2C is a slave.

2C is a master.

Table 40-6. I2C Parameter RAM Memory Map

Offset 1

Name

Width

Description

0x00

RBASE

Hword Rx/TxBD table base address. Indicate where the BD tables begin in the dual-port RAM.

Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are

allocated for the Tx and Rx sections of the I

2C. Initialize RBASE/TBASE before

enabling the I2C. Furthermore, do not configure BD tables of the I2C to overlap any

other active controller’s parameter RAM. RBASE and TBASE should be divisible by

eight.

0x02

TBASE

Hword

0x04

RFCR

Byte

Rx/Tx function code registers. The function code registers contain the transaction

specification associated with SDMA channel accesses to external memory. See

Figure 40-11 and Table 40-7.

0x05

TFCR

Byte

0x06

MRBLR

Hword Maximum receive buffer length. Defines the maximum number of bytes the MPC8280

writes to a Rx buffer before moving to the next buffer. The MPC8280 writes fewer bytes

to the buffer than the MRBLR value if an error or end-of-frame occurs. Buffers should

not be smaller than MRBLR.

Tx buffers are unaffected by MRBLR and can vary in length; the number of bytes to be

sent is specified in TxBD[Data Length].

MRBLR is not intended to be changed while the I

2C is operating. However it can be

changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles

back-to-back). The change takes effect when the CP moves control to the next RxBD.

To guarantee the exact RxBD on which the change occurs, change MRBLR only while

the I2C receiver is disabled. MRBLR should be greater than zero; it should be an even

number if the character length of the data exceeds 8 bits.

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