MPC8280 datasheet(1309/1386 Pages) FREESCALE

1309 / 1386 page

2C Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

40-7

40.4.2

I2C Address Register (I2ADD)

The I2C address register, shown in Figure 40-7, holds the address for this I2C port.

Table 40-2 describes I2ADD fields.

40.4.3

I2C Baud Rate Generator Register (I2BRG)

The I2C baud rate generator register, shown in Figure 40-8, sets the divide ratio of the I2C BRG.

Table 40-3 describes I2BRG fields.

40.4.4

I2C Event/Mask Registers (I2CER/I2CMR)

The I2C event register (I2CER) is used to generate interrupts and report events. When an event is

recognized, the I2C controller sets the corresponding I2CER bit. I2CER bits are cleared by writing ones;

writing zeros has no effect. Setting a bit in the I2C mask register (I2CMR) enables and clearing a bit masks

Field

SAD

—

Reset

Undefined

R/W

Addr

0x11864

Figure 40-7. I2C Address Register (I2ADD)

Table 40-2. I2ADD Field Descriptions

Bits

Name

Description

0–6

SAD

Slave address 0–6. Holds the slave address for the I

2C port.

—

Reserved and should be cleared.

Field

DIV

Reset

1111_1111

R/W

Addr

0x11868

Figure 40-8. I2C Baud Rate Generator Register (I2BRG)

Table 40-3. I2BRG Field Descriptions

Bits

Name

Description

0–7

DIV

Division ratio 0–7. Specifies the divide ratio of the BRG divider in the I

2C clock generator. The output

of the prescaler is divided by 2 * ([DIV0–DIV7] + 3 + (2 * I2MOD[FLT])) and the clock has a 50% duty

cycle. DIV must be programmed to a minimum value of 3 if the digital filter is disabled

(I2MOD[FLT] = 0) and 6 if it is enabled (I2MOD[FLT] = 1) .

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