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HE84G762B Datasheet(PDF) 49 Page - King blillion Electronics Co.,Ltd. |
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HE84G762B Datasheet(HTML) 49 Page - King blillion Electronics Co.,Ltd. |
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49 / 60 page  KING BILLION ELECTRONICS CO., LTD 駿 億 電 子 股 份 有 限 公 司 HE84G762B HE80004 Series June 1, 2004 49 V0.92 This specification is subject to change without notice. Please contact sales person for the latest version before use. RATE BAUD FCK DIVISOR RATE BAUD _ * 16 _ _ = , (FCK: fast clock of system) The contents of BRH and BRL are calculated by the following two formulas: BRL = DIVISOR RATE BAUD _ _ % 256 BRH = ( DIVISOR RATE BAUD _ _ – BRL) / 256 The “%” symbol is the modulus operation (reminder of division). For example, if the FCK is 1.8432M Hz and the desired baud rate is 2400 baud, then 48 2400 * 16 1843200 _ _ = = DIVISOR RATE BAUD The BRL register shall be set to 0x30 and BRH set to 0x00. The setting of baud_rate_divisor is not updated until the BRH register is written. Thus user is strongly recommended to write BRL first, then BRH. In order to obtain good communication quality, the same time base shall be used in the both sides of transmitting and receiving. The following table shows the most common baud rate setting used in the PC UART communication. BRL and BRH: Baud Rate Control Registers FCK(Hz) Baud Rate (bps) Divisor BRL BRH 1.8432M 50 2304 0x00 0x09 1.8432M 300 384 0x80 0x01 1.8432M 1200 96 0x60 0x00 1.8432M 2400 48 0x30 0x00 1.8432M 4800 24 0x18 0x00 1.8432M 9600 12 0x0C 0x00 1.8432M 19200 6 0x06 0x00 1.8432M 38400 3 0x03 0x00 1.8432M 57600 2 0x02 0x00 1.8432M 115200 1 0x01 0x00 21.3. Interrupt & Identification Register This high nibble of IEIR register allows to enable/disable interrupt generation by the UART, the low nibble ID[2..0] of IEIR register is used to identify the source of interrupts. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Value 0x02h IEIR 0 RLSI THRI RBRI 0 ID2 ID1 ID0 “0000_0000” - R/W R/W R/W - R R R RBRI: Receiver Buffer Register Interrupt (1 = Enable, 0 = Disable), related to ID[1] bit. THRI: Transmitter Hold Register Interrupt (1 = Enable, 0 = Disable), related to ID[0] bit. RLSI: Receiver Line Status Interrupt (1 = Enable, 0 = Disable), related to ID[2] bit. |
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