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ACT2861 Datasheet(PDF) 40 Page - Qorvo, Inc |
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ACT2861 Datasheet(HTML) 40 Page - Qorvo, Inc |
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40 / 97 page ![]() Data Sheet Rev. F, April 2022 | Subject to change without notice 40 of 97 www.qorvo.com © 2020 Qorvo US, Inc. All rights reserved. Confidential ACT2861 30V Buck-Boost Charger with Integrated MOSFETs and OTG ® Battery Full / Charging Termination The ACT286x terminates a charge cycle when the bat- tery reaches the termination voltage and the charge cur- rent drops below the termination current. If the Input cur- rent limit, Input Voltage limit, or Thermal Regulation loop is active, the charger will not enter the Charge Full or Charge Termination states. Once the termination current and other requirements are met, the charger transitions from the fast charge state (FASTCHG) into either the charge full state (CHGFULL) or charge termination state (CHGTERM). When EN_TERM=0, the charger enters the CHGFULL state. The Charge Full state functionality is the same as the FASTCHG state. The charger can stay in the CHGFULL state indefinitely. It keeps a fully charged battery regulated to the VBAT_REG voltage. If some- thing pulls current from the battery, the charger supplies current to maintain the battery voltage at VBAT_REG. The maximum charge current is still limited by the ex- ternal OLIM resistor and the IFCHG[6:0] register. When EN_TERM=1, the charger enters the CHGTERM state. In this state, the charger is disabled and does not supply any current to the battery. It monitors the battery voltage to check for the condition when the battery volt- age drops below VTERM-VRECHARGE. The VRECHARGE voltage is typically 100mV or 150mV per cell. Once the battery voltage drops below the threshold, the IC enters the Fast Charge state and recharges the battery. See the state machine for more details charging and charge termination. Charging Safety Timers The ACT2861 provides two internal charging safety tim- ers: Low Battery Safety Timer and Fast Charge Safety Timer When the Battery Voltage is below VBAT_LOW and in the charger is in the SCOND or PCOND states, a fixed 120 minute Low Battery Safety Timer is implemented. Dur- ing this time, the Fast Charge Safety Timer is held in reset and not active. If the Low Battery Safety timer times out, the IC goes to the Charging Fault state until it is reset – See below on how to clear the Low Battery Safety Timer. The Low Battery Safety Timer stops if the battery tem- perature causes the converter to stop switching and en- ter the SCSUSPEND or PCSUSPEND states. The Low Battery Safety Timer runs at ½ speed if the Input Volt- age, Input Current, or Die Temperature regulations loops become active. This increases the overall time of 120 minute timer. When the Battery Voltage is above VBAT_LOW the Fast Charge Safety Timer is enabled and the Low Battery Safety timer is held in reset. The Fast Charge Safety Timer is controlled with the I2C bits FC_SAFETY_TIMER[4:0] in register 0x1Bh. It is config- urable between 30 minutes and 16 hours. If the Fast Charge safety timer expires, the IC goes into the Charg- ing Fault state and charging is disabled until the Fast Charge Safety Timer is reset. Both the Low Battery Safety and Fast Charge Safety Timers can be fully disabled and reset via the I2C bit DIS_SAFETY_TIMER in register 0x1Bh or manually suspended using the I2C bit SUS- PEND_SAFETY_TIMER in register 0x1Bh. Both safety timers are automatically stopped any time the charging is enabled but charging has suspended. This occurs when the battery temperature exceeds the allowable temperature limits. Both safety timers also run at ½ speed when VIN Input Regulation, IIN Current Regulation, or Die Thermal Regulation are active to increase the overall safety timer windows. Additionally, the Fast Charge Safety Timer runs at ½ speed in some JEITA charging modes. See the JEITA Battery Temperature Control paragraph for more details. Both safety timers are reset when any of the following occur: 1. Charging State Machine enters RESET state 2. DIS_SAFETY_TIMER register is set High 3. Charging has completed. This includes enter- ing either the CHGFULL or CHG TERM states. 4. IC exits the Charge Mode via the EN_CHG pin, OVERRIDE_EN_CHG, HIZ Registers, etc. |
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