PIC16F18323-ESLASHRF datasheet(124/442 Pages) MICROCHIP

124 / 442 page

PIC16(L)F18313/18323

DS40001799A-page 124

Preliminary

 2015 Microchip Technology Inc.

NVMCON1: NONVOLATILE MEMORY CONTROL 1 REGISTER

U-0

R/W-0/0

R/W/HC-0/0

R/W/HS-x/q

R/W-0/0

R/S/HC-0/0

—

NVMREGS

LWLO

FREE

WRERR

WREN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

S = Bit can only be set

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

HC = Bit is cleared by hardware

bit 7

Unimplemented:

Read as ‘0’

bit 6

NVMREGS:

Configuration Select bit

= Access EEPROM, Configuration, User ID and Device ID Registers

= Access Program Flash Memory

bit 5

LWLO:

Load Write Latches Only bit

When FREE = 0:

= The next WR command updates the write latch for this word within the row; no memory operation is initiated

= The next WR command writes data or erases

Otherwise: The bit is ignored.

bit 4

FREE:

Program Flash Memory Erase Enable bit

When NVMREGS:NVMADR points to a Program Flash Memory location:

= Performs an erase operation with the next WR command; the 32-word pseudo-row containing the indicated

address is erased (to all 1s) to prepare for writing

= All write operations have completed normally

bit 3

WRERR:

Program/Erase Error Flag bit (1,2,3)

This bit is normally set by hardware.

= A write operation was interrupted by a Reset, or WR was written to one while NVMADR points to a

write-protected address.

= The program or erase operation completed normally

bit 2

WREN:

Program/Erase Enable bit

= Allows program/erase cycles

= Inhibits programming/erasing of program Flash

bit 1

WR:

Write Control bit(4,5,6)

When NVMREG:NVMADR points to a EEPROM location:

= Initiates an erase/program cycle at the corresponding EEPROM location

= NVM program/erase operation is complete and inactive

When NVMREG:NVMADR points to a Program Flash Memory location:

= Initiates the operation indicated by Table 10-4

= NVM program/erase operation is complete and inactive

Otherwise: This bit is ignored.

bit 0

RD:

Read Control bit(7)

= Initiates a read at address = NVMADR1, and loads data to NVMDAT Read takes one instruction cycle and the

bit is cleared when the operation is complete. The bit can only be set (not cleared) in software.

= NVM read operation is complete and inactive

Note

Bit is undefined while WR = 1 (during the EEPROM write operation it may be ‘0’ or ‘1’).

Bit must be cleared by software; hardware will not clear this bit.

Bit may be written to ‘1’ by software in order to implement test sequences.

This bit can only be set by following the unlock sequence of Section 10.4.2 “NVM Unlock Sequence”.

Operations are self-timed, and the WR bit is cleared by hardware when complete.

Once a write operation is initiated, setting this bit to zero will have no effect.

Reading from EEPROM loads only NVMDATL<7:0> (Register 10-1).

PIC16F18323-E/RF Datasheet(PDF) 124 Page - Microchip Technology

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