MPC8358E datasheet(34/96 Pages) FREESCALE

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MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1

Freescale Semiconductor

UCC Ethernet Controller: Three-Speed Ethernet, MII Management

8.2.5

RGMII and RTBI AC Timing Specifications

Table 34 presents the RGMII and RTBI AC timing specifications.

Table 34. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with LVDD of 2.5 V ± 5%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

Data to clock output skew (at transmitter)

tSKRGTKHDX

tSKRGTKHDV

–0.5

—

——

0.5

Data to clock input skew (at receiver)

tSKRGDXKH

tSKRGDVKH

1.1

—

——

2.6

Clock cycle duration

tRGT

7.2

8.0

8.8

Duty cycle for 1000Base-T

tRGTH/tRGT

4, 5

Duty cycle for 10BASE-T and 100BASE-TX

tRGTH/tRGT

3, 5

Rise time (20%–80%)

tRGTR

—

0.75

Fall time (20%–80%)

tRGTF

—

0.75

GTX_CLK125 reference clock period

tG125

—8.0

—

GTX_CLK125 reference clock duty cycle

tG125H/tG125

—

Notes:

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the

notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,

the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

will be added to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as

long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed

transitioned between.

5. Duty cycle reference is LVDD/2.

6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.7.In

rev2.1 silicon, due to errata, tSKRGTKHDX minimum is -0.65 ns for UCC2 option 1 and -0.9 for UCC2 option 2, and tSKRGTKHDV

maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2 option 2. Please refer to

QE_ENET10 in the device

errata document. UCC1 does meet tSKRGTKHDX minimum for rev2.1 silicon.

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