MPC8358E datasheet(63/96 Pages) FREESCALE

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MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1

Freescale Semiconductor

HDLC, BISYNC, Transparent, and Synchronous UART

Figure 47 provides the AC test load.

Figure 47. AC Test Load

19.3

AC Test Load

Figure 48 and Figure 49 represent the AC timing from Table 61 and Table 62. Note that although the

specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when

the falling edge is the active edge.

Table 62. Synchronous UART AC Timing Specifications1

Characteristic

Symbol2

Min

Max

Unit

Outputs—Internal clock delay

tUAIKHOV

11.3

Outputs—External clock delay

tUAEKHOV

114

Outputs—Internal clock High Impedance

tUAIKHOX

011

Outputs—External clock High Impedance

tUAEKHOX

114

Inputs—Internal clock input setup time

tUAIIVKH

6—

Inputs—External clock input setup time

tUAEIVKH

8—

Inputs—Internal clock input Hold time

tUAIIXKH

1—

Inputs—External clock input hold time

tUAEIXKH

1—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high

state (H) until outputs (O) are invalid (X).

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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