MPC8358E datasheet(91/96 Pages) FREESCALE

91 / 96 page

MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1

Freescale Semiconductor

System Design Information

24.1

System Clocking

The device includes two PLLs.

1. The platform PLL (AVDD1) generates the platform clock from the externally supplied CLKIN

input. The frequency ratio between the platform and CLKIN is selected using the platform PLL

ratio configuration bits as described in Section 22.1, “System PLL Configuration.”

2. The e300 core PLL (AVDD2) generates the core clock as a slave to the platform clock. The

frequency ratio between the e300 core clock and the platform clock is selected using the e300

PLL ratio configuration bits as described in Section 22.2, “Core PLL Configuration.”

24.2

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,

AVDD2 respectively). The AVDD level should always be equivalent to VDD, and preferably these voltages

will be derived directly from VDD through a low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide five independent filter circuits as illustrated in Figure 53, one to each of the five AVDD pins. By

providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the

other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz

range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a

single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize

noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD

pin, which is on the periphery of package, without the inductance of vias.

Figure 53 shows the PLL power supply filter circuit.

Figure 53. PLL Power Supply Filter Circuit

24.3

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient

power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the device system, and the device itself

requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer

place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the device. These

decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND

VDD

AVDDn

2.2 µF

GND

Low ESL Surface Mount Capacitors

MPC8358E Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc

MPC8358E Datasheet(HTML) 91 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL