MPC8358E datasheet(75/96 Pages) FREESCALE

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MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1

Freescale Semiconductor

Clocking

parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.The

OCCR[PCIOENn] parameters enable the PCI_CLK_OUTn respectively.

PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subystem to

synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,

with equal delay to all PCI agent devices in the system, to allow the device to function. When the device

is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured

as a PCI agent device the CLKIN and the CFG_CLKIN_DIV signals should be tied to GND.

When the device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is

disabled (RCWH[PCICKEN] = 0), clock distribution and balancing done externally on the board.

Therefore, PCI_SYNC_IN is the primary input clock.

As shown in , the primary clock input (frequency) is multiplied by the QUICC Engine block phase-locked

loop (PLL), the system PLL, and the clock unit to create the QUICC Engine clock (ce_clk), the coherent

system bus clock (csb_clk), the internal DDRC1 controller clock (ddr1_clk), and the internal clock for the

local bus interface unit and DDR2 memory controller (lb_clk).

The csb_clk frequency is derived from a complex set of factors that can be simplified into the following

equation:

csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF

In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency; in PCI agent

mode, CFG_CLKIN_DIV must be pulled down (low), so PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is

the PCI_CLK frequency.

The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up

the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL

multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL)

which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4, “Reset,

Clocking, and Initialization,” in the MPC8360E Integrated Communications Processor Reference

Manual, Rev. 2 for more information on the clock subsystem.

The ce_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF)

and the QUICC Engine PLL division factor (RCWL[CEPDF]) according to the following equation:

ce_clk = (primary clock input × CEPMF)

÷ (1 + CEPDF)

The internal ddr1_clk frequency is determined by the following equation:

ddr1_clk = csb_clk × (1 + RCWL[DDR1CM])

Note that the lb_clk clock frequency (for DDRC2) is determined by RCWL[LBCM]. The internal

ddr1_clk frequency is not the external memory bus frequency; ddr1_clk passes through the DDRC1 clock

divider (

÷2) to create the differential DDRC1 memory bus clock outputs (MEMC1_MCK and

MEMC1_MCK). However, the data rate is the same frequency as ddr1_clk.

The internal lb_clk frequency is determined by the following equation:

lb_clk = csb_clk × (1 + RCWL[LBCM])

MPC8358E Datasheet(PDF) 75 Page - Freescale Semiconductor, Inc

MPC8358E Datasheet(HTML) 75 Page - Freescale Semiconductor, Inc

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