WS9623AB3DF

Datasheet (V1.2)

Copyright © Vimicro_wx, Inc. 1999-2014

12

cable, seven wires are present. Only the ring indicator RI and carrier detect CD signal are not linked. The cable is

shown in the following figure. DTR and DSR are not used in UART of WS9623AB3DF.

Figure 6 Null Modem Cable Connections

Connector 1

Connector 2

Function

2

3

Rx

Tx

3

2

Tx

Rx

4

6

DTR

DSR

5

5

Signal ground

6

4

DSR

DTR

7

8

RTS

CTS

8

7

CTS

RTS

In CTS/RTS flow, the RTS output of device1 signals device2 that device1 is capable of receiving information, so

device2 will send the data out when the RTS signal of device1 is set valid. Also, device1 will send the data out

when the RTS signal of device2 is set valid.

I

2C Interface

WS9623AB3DF provides PROM_SCL and PROM_SDA for communication with EEPROM which comply with I

2C

protocol.

I

2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of data exchange between

devices. It is most suitable for applications requiring occasional communication over a short distance between

many devices. The I

2C standard is a true multi-master bus including collision detection and arbitration that

prevents data corruption if two or more masters attempt to control the bus simultaneously.

The I

2C interface defines 2 transmission speeds:



Normal: 100Kbit/s



Fast: 400Kbit/s

Only 100Kbps mode and 400Kbps mode are supported directly.

FEATURES:



Compatible with I

2C standard;



Multi Master Operation;



Supports 7 and 10bit addressing mode;



Software programmable clock frequency, supports a wide range of input clock frequencies;



Software programmable acknowledge bit;



Interrupt or bit-polling driven byte-by-byte data-transfers;



Arbitration lost interrupt, with automatic transfer cancellation;



Bus busy detection;



Clock Stretching and Wait state generation;