WS9623AB3DF

Datasheet (V1.2)

Copyright © Vimicro_wx, Inc. 1999-2014

14

direction specified by the RW bit that sent by the master. Each transferred byte is followed by an acknowledge bit

on the 9th SCL clock cycle. If the slave signals a No Acknowledge, the master will generate a STOP signal to abort

the data transfer, or generate a Repeated START signal and then start a new transfer cycle.

If the master, as the receiving device, does not acknowledge the slave, the slave should release the SDA line for

the master to generate a STOP or Repeated START signal.

To write data to a slave, store the data in the Transmit Register to be transmitted and set the WR bit. To read data

from a slave, set the RD bit. The core set the TIP flag during a transfer, indicating that a transfer is in progress.

When the transfer is done the TIP flag is reset, and generates an interrupt. The Receive Register contains valid

data after the IF flag is reset. The user may issue a new write or read command when the TIP flag is reset.

STOP Signal

The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred as the

P-bit, is defined as a low-to-

high transition of SDA while SCL is at logical „1‟.

Arbitration Procedure



Clock Synchronization

The I

2C bus is a true multi-master bus that allows more than one master to be connected on it. If two or more

masters simultaneously try to control the bus, a clock synchronization procedure determines the bus clock.

Because of the wired-AND connection of the I

2C signals, a high-to-low transition affects all the devices that

connected to the bus. Therefore a high

–to-low transition on the SCL line causes all concerned devices to count off

their low period. Once a device clock has gone low, it will hold the SCL line in low state until the clock high state is

reached. Due to the wired-AND connection, the SCL line will therefore be held low by the device with the longest

low period, and held high by the device with the shortest high period.

Figure 8 Arbitration Procedure



Clock Stretching

Slave devices can use the clock synchronization mechanism to slow down the transfer bit rate. After the master

has driven SCL low, the slave can drive SCL low for the required period and then release it. If the slave‟s SCL low

period is greater than the ma

ster‟s SCL low period, the resulting SCL bus signal low period will be stretched, thus

inserting wait-states.

GPIO interface

The ports GPIO [15:1] / GPIO_A/ GPIO_B are general purpose IO, GPIO [15:13] / GPIO_B are used as LED.

GPIO [12:1] / GPIO_A are used as Buttons which indicate volume control, music play/stop, link statues display, etc.

The special function of each port can be configured in SW.

GPIO [4:1] is shared for UART connections. GPIO [4:1] is used for UART transport by configuring related register

by SW.

The PWR is voltage value high indication port and it is used as Multi function port. High level (BAT voltage) of this

port means the button is turned on; it can be used for powering on, powering down, or paging scan mode of chip

according of its high level and Duration of High level.

There are 17 GPIO in the GPIO module. GPIO module is used to process the transmission and receiving between

GPIO pad and the core and to generate the interrupt from GPIO pad.

Start counting

low period

wait

state

Start counting

high period

SCL1

SCL2

SCL

Master1 SCL

Master2 SCL

wired-AND SCL