WS9623AB3DF

Datasheet (V1.2)

Copyright © Vimicro_wx, Inc. 1999-2014

13

Interface Timing Signal with I

2C bus

System Configuration

The I

2C system uses the serial data line (SDA) and serial clock line (SCL) for data transfers. All devices connected

to these two signals must have open drain or collector outputs. The logic AND function is exercised on both lines

with external pull-up resistors.

Data is transferred between a Master and a Slave synchronously to SCL on the SDA line via a byte-by-byte basis.

Each data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB being transmitted first.

An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the

SDA line may be changed only during the low period of SCL and it must be held stable during the high period of

SCL. While SCL is high, the transition on the SDA line is interpreted as a command (sees START and STOP

signals).

I

2C Protocol

Generally, a standard communication consists of four parts:



START signal generation



Slave address transfer



Data transfer



STOP signal generation

Figure 7 I

2C protocol

START Signal

When the bus is free/idle, that is no master device is engaging the bus (both SCL and SDA lines are high), a

master can initiate a transfer by sending a START signal. The START signal, usually referred as the S-bit, is

defined as a high-to-low transition of SDA while SCL is high. The START signal denotes the beginning of a new

data transfer.

Repeated START is a START signal without first generating a STOP signal. The master uses this method to

communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to

reading from a device) without releasing the bus.

The core generates a START signal when the STA-bit in the Command Register is set and the RD or WR bits are

set. Depending on the current status of the SCL line, a START or Repeated START is generated.

Slave Address Transfer

The slave address is the first byte of data transferred by the master immediately after the START signal. This is a

seven-bits calling address followed by a RW bit. The RW bit signals the slave data transfer direction. The slave

address is unique; no two slaves in the system can have the same address. Only the slave with an address that

matches the address transmitted by the master will respond, it responds by returning an acknowledge bit which is

pulled by the SDA low at the 9th SCL clock cycle.

Note: The core supports 10bit slave addresses by generating two address transfers. See the Philips I

2C

specifications for more details.

The core treats a Slave Address Transfer as any other writ

e action. Store the slave device‟s address in the

Transmit Register and set the WR bit. The core will then transfer the slave address on the bus.

Data Transfer

Once achieved the successful slave addressing, the data transfer can proceed on a byte-by-byte basis in the

S

A7 A6 A5 A4 A3 A2 A1

ack D7 D6 D5 D4 D3 D2 D1 D0 nack P

R

W

9

7

6

5

4

3

2

1

8

9

7

6

5

4

3

2

1

8