STM32WBA62CG datasheet(46/185 Pages) STMICROELECTRONICS

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Functional overview

STM32WBA6xxx

46/185

DS14736 Rev 1

3.18

Interrupts and events

3.18.1

Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller (NVIC) that is able to manage 16

priority levels and to handle up to 70 maskable interrupt vectors plus the 16 interrupt vectors

of the Cortex-M33.

The NVIC benefits are the following:

•

closely coupled NVIC giving low-latency interrupt processing

•

interrupt entry vector table address passed directly to the core

•

early processing of interrupts

•

processing of late arriving higher priority interrupts

•

support for tail chaining

•

processor state automatically saved

•

interrupt entry restored on interrupt exit with no instruction overhead

•

TrustZone support: NVIC registers banked across secure and nonsecure states

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.18.2

Extended interrupt/event controller (EXTI)

The extended interrupts and event controller (EXTI) manages the individual CPU and

system wake-up through configurable event inputs. It provides wake-up requests to the

Table 11. GPDMA1 channels implementation and usage

Channel x

Hardware parameters

Features

dma_fifo_

size[x]

dma_

addressing[x]

x = 0 to 5

Channel x is implemented with:

– a FIFO of 8 bytes, 2 words

– fixed/contiguously incremented addressing

These channels may be also used for GPDMA transfers,

between an APB or AHB peripheral and SRAM.

x = 6 to 7

Channel x is implemented with:

– a FIFO of 32 bytes, 8 words

– fixed/contiguously incremented addressing

These channels may be also used for GPDMA transfers,

between a demanding AHB or APB peripheral and

SRAM.

Table 12. GPDMA1 autonomous mode and wake-up in low-power modes

Feature

Low-power modes

Autonomous mode and wake-up

Sleep, Stop 0 modes

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