STM32WBA62CG datasheet(40/185 Pages) STMICROELECTRONICS

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Functional overview

STM32WBA6xxx

40/185

DS14736 Rev 1

3.12.3

Reset mode

To improve the consumption under reset, the I/Os state under and after reset is “analog

state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is

deactivated when the reset source is internal.

3.12.4

PWR TrustZone security

When TrustZone security is activated by the TZEN option bit, the PWR is switched in

TrustZone security mode.

The PWR TrustZone security secures the following configuration:

•

Low-power mode

•

WKUP (wake-up) pins

•

Voltage detection

•

Backup domain control

Some of the PWR configuration bits security is defined by the security of other peripherals:

•

The VOS (voltage scaling) configuration is secure when the system clock selection is

secure in RCC.

•

The I/O Standby mode retention configuration is secure when the corresponding GPIO

is secure.

3.13

Reset and clock controller (RCC)

The RCC (reset and clock controller) manages device and peripheral reset and distributes

the clocks coming from the different oscillators to the core and to the peripherals. It also

manages the clock gating for low-power modes and ensures the clock robustness. It

features:

7. PTACONV interface signal levels can be retained on GPIOs.

8. Some peripherals with autonomous mode and wake-up from Stop capability can request HSI16 to be

enabled. In this case, the oscillator is woken up by the peripheral, and is automatically put off when no

peripheral needs it.

9. The 2.4 GHz RADIO peripheral in autonomous mode request HSE32 to be enabled. In this case, the

oscillator is kept active by the peripheral, and is automatically put off when it no longer needs it.

10. I/O levels can be retained with pull-up, pull-down, or floating.

11. There are 16 wake-up pins available.

12. UART and LPUART reception and transmission are functional and autonomous in Stop mode in

asynchronous and in SPI master modes, and generate a wake-up interrupt on transfer events.

13. I2C reception and transmission is functional and autonomous in Stop mode and generates a wake-up

interrupt on transfer events.

14. SPI reception and transmission is functional and autonomous in Stop mode and generates a wake-up

interrupt on transfer events.

15. A/D conversion is functional and autonomous in Stop mode, and generates a wake-up interrupt on

conversion events.

16. LPTIM is functional and autonomous in Stop mode, and generates a wake-up interrupt on events.

17. GPDMA transfers are functional and autonomous in Stop 0 mode, and generates a wake-up interrupt on

transfer events.

18. DBGMCU remains accessible trough AP0.

19. DBGMCU remains accessible through AP0 when CDBGPWRUPREQ is set.

STM32WBA62CG Datasheet(PDF) 40 Page - STMicroelectronics

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