STM32WBA62CG datasheet(17/185 Pages) STMICROELECTRONICS

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DS14736 Rev 1

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STM32WBA6xxx

Functional overview

3.1

Arm Cortex-M33 core with TrustZone, MPU, DSP, and FPU

The Cortex-M33 with TrustZone, MPU, DSP and FPU is a highly energy-efficient processor

designed for microcontrollers and deeply embedded applications, especially those requiring

efficient security.

The Cortex-M33 processor delivers a high computational performance with low-power

consumption and an advanced response to interrupts. It features:

•

Arm TrustZone technology, using the Armv8-M main extension supporting secure and

nonsecure states

•

MPUs (memory protection units), supporting up to 16 regions for secure and nonsecure

applications

•

Configurable SAU (secure attribute unit) supporting up to eight memory regions as

secure or nonsecure

•

Floating-point arithmetic functionality with support for single precision arithmetic

The processor supports a set of DSP instructions that allows an efficient signal processing

and a complex algorithm execution.

The Cortex-M33 processor supports the following bus interfaces:

•

System AHB (S-AHB) bus: used for any instruction fetch and data access to the

memory-mapped SRAM, peripheral, and Vendor_SYS regions of the Armv8-M memory

map.

•

Code AHB (C-AHB) bus: used for any instruction fetch and data access to the code

region of the Armv8-M memory map.

3.2

ART Accelerator (ICACHE)

The ICACHE (instruction cache) is introduced on C-AHB code bus of Cortex-M33 processor

to improve performance when fetching instruction (or data) from internal memories.

ICACHE offers the following features:

•

Multibus interface:

–

Slave port receiving the memory requests from the Cortex-M33 C-AHB code

execution port

–

Master1 port performing refill requests to internal flash memory

–

Master2 port performing refill requests to internal SRAM memories

–

Second slave port dedicated to ICACHE registers access

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