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STM32WBA62CG Datasheet(PDF) 19 Page - STMicroelectronics |
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STM32WBA62CG Datasheet(HTML) 19 Page - STMicroelectronics |
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19 / 185 page ![]() DS14736 Rev 1 19/185 STM32WBA6xxx Functional overview 69 3.5 Embedded flash memory The devices feature an up to 2-Mbyte embedded flash memory, available to store programs and data. This memory supports 10000 cycles, and up to 100000 cycles on 64 pages (512 Kbytes). A 128-bit instruction prefetch is implemented and can optionally be enabled. The flash memory interface features dual-bank operation modes and read-while-write (RWW), hence a read operation to be performed from one bank while an erase or program operation is performed on the other bank. The dual-bank boot is also supported. Each bank contains up to 128 pages of 8 Kbytes. The flash memory also embeds a 512-byte one-time programmable (OTP) memory for user data. The whole nonvolatile memory embeds the error correction code (ECC) feature supporting: • single-error detection and correction • double-error detection • ECC fail address report 3.5.1 Flash memory protections The user options allow the configuration of flexible protections: • write protection (WRP) to protect areas against erasing and programming. Two areas per bank can be selected with 8-Kbyte granularity • readout protection (RDP) to protect the whole memory, has four levels of protection available (see Table 3 and Table 4): – Level 0: no readout protection – Level 0.5: available only when TrustZone is enabled All read/write operations (if no write protection is set) from/to the nonsecure flash memory are possible. The debug access to secure area is prohibited. Debug access to nonsecure area remains possible. – Level 1: memory readout protection The flash memory cannot be read from or written to if either the debug features are connected or the boot in RAM or bootloader are selected. If TrustZone is enabled, the nonsecure debug is possible and the boot in SRAM is not possible. Regressions from Level 1 to lower levels can be protected by password authentication. – Level 2: chip readout protection The debug features, the boot in RAM and the bootloader selection are disabled. A secure secret key can be configured in the secure options to allow the regression capability from Level 2 to Level 1. By default (key not configured), this Level 2 selection is irreversible and JTAG/SWD interfaces are disabled. If the secret key was previously configured in lower RDP levels, the device enables the RDP regression from Level 2 to Level 1 after password authentication through JTAG/SWD interface. Note: To reach the best protection level, it is recommended to activate TrustZone and to set RDP level 2 with password authentication regression enabled. |
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