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STM32WBA62CG Datasheet(PDF) 21 Page - STMicroelectronics

Part # STM32WBA62CG
Description  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M33 with TrustZone , FPU, Bluetooth IEEE802.15.4 radio solution
PDF  185 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WBA62CG Datasheet(HTML) 21 Page - STMicroelectronics

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STM32WBA6xxx
Functional overview
69
3.5.2
Additional flash memory protections when TrustZone is activated
When the TrustZone security is enabled through option bytes, the whole flash memory is
secure after reset and the following protections are available:
•
Nonvolatile watermark-based secure flash memory area
The secure area can be accessed only in Secure mode. One area can be selected with
a page granularity.
•
Secure hide protection area (HDP)
It is part of the flash memory secure area and can be protected to deny access to this
area by any data read, write, and instruction fetch. For example, a software code in the
secure flash memory hide protection area can be executed only once and deny any
further access to this area until the next system reset. One area can be selected at the
beginning of the secure area.
•
Volatile block-based secure flash memory area
Each page can be programmed on-the-fly as secure or nonsecure.
3.5.3
FLASH privilege protection
Each flash memory page can be programmed on-the-fly as privileged or unprivileged.
OTP
0.5
Yes
Yes(7)
N/A
Yes
Yes(7)
N/A
1Yes
Yes(7)
N/A
Yes
Yes(7)
N/A
2Yes
Yes(7)
N/A
N/A
N/A
N/A
Backup registers
0.5
Yes
Yes
N/A
Yes(2)
Yes(2)
N/A(8)
1
Yes
Yes
N/A
No
No
N/A(8)
2
Yes
Yes
N/A
N/A
N/A
N/A
SRAM2
0.5
Yes
Yes
N/A
Yes(2)
Yes(2)
N/A(9)
1
Yes
Yes
N/A
No
No
N/A(9)
2
Yes
Yes
N/A
N/A
N/A
N/A
1. When the protection level 2 is active, the debug port and the bootloader mode are disabled.
2. Depends on TrustZone security access rights.
3. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
4. Option bytes are only accessible through the flash registers interface and OPSTRT bit.
5. The flash main memory is erased when the RDP option byte regresses from level 1 to level 0.
6. SWAP_BANK user option can be modified.
7. OTP can be written only once.
8. The backup registers are erased when RDP changes from level 1 to level 0.
9. All SRAMs are erased when RDP changes from level 1 to level 0.
Table 4. Access status versus protection level and execution modes when TZEN = 1 (continued)
Area
RDP
level
User execution
(boot from flash memory)
Debug/bootloader(1)
Read
Write
Erase
Read
Write
Erase



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