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STM32WBA62CG Datasheet(PDF) 22 Page - STMicroelectronics

Part # STM32WBA62CG
Description  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M33 with TrustZone , FPU, Bluetooth IEEE802.15.4 radio solution
PDF  185 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WBA62CG Datasheet(HTML) 22 Page - STMicroelectronics

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Functional overview
STM32WBA6xxx
22/185
DS14736 Rev 1
3.6
Embedded SRAMs
SRAM1 and SRAM2 are the main embedded SRAMs, each with specific features. These
memories can be used for peripherals background autonomous mode (BAM).
The SRAMs can be powered down in Stop mode to reduce consumption:
•
SRAM1: up to seven 64-Kbyte blocks (up to 448 Kbytes), can be retained in Standby
mode
•
SRAM2: one 64-Kbyte block with parity, can be retained in Standby mode.
3.6.1
SRAMs TrustZone security
When TrustZone security is enabled, SRAMs are secure after reset. SRAM1 and SRAM2
can be programmed as secure or nonsecure by blocks, using the block-based memory
protection controller (MPCBB).
The granularity of SRAM secure block based is a page of 512 bytes.
3.6.2
SRAMs privilege protection
The SRAM1 and SRAM2 can be programmed as privileged or unprivileged by blocks, using
the MPCBB. The granularity of SRAM block-based privilege is a page of 512 bytes.
3.7
TrustZone security architecture
The security architecture is based on Arm TrustZone with the Armv8-M main extension.
The TZEN option bit in the FLASH_OPTR register activates the TrustZone security.
When TrustZone is enabled, the SAU (security attribution unit) and IDAU (implementation
defined attribution unit) define the access permissions based on secure and nonsecure
state.
•
SAU: up to eight SAU configurable regions are available for security attribution.
•
IDAU: provides a first memory partition as nonsecure or nonsecure callable attributes.
It is then combined with the results from the SAU security attribution and the higher
security state is selected.
Based on IDAU security attribution, the flash memory, system SRAM and peripheral
memory space is aliased twice for secure and nonsecure states.
Table 5 shows an example of typical SAU regions configuration based on IDAU regions.
Table 5. Example of memory map security attribution versus SAU configuration regions
Region description
Address range
IDAU security
attribution
SAU security
attribution typical
configuration
Final security
attribution
ICACHE Re-mappable
(Reserved)
0x0000 0000
0x07FF FFFF
Nonsecure
Secure or nonsecure or nonsecure callable
Code
flash memory and SRAM
0x0800 0000
0x0BFF FFFF
Nonsecure
0x0C00 0000
0x0FFF FFFF
Nonsecure callable
Secure or NSC



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