STM32WBA62CG datasheet(18/185 Pages) STMICROELECTRONICS

18 / 185 page

Functional overview

STM32WBA6xxx

18/185

DS14736 Rev 1

•

Close to 0 wait-states instructions/data access performance:

–

0 wait-states on cache hit

–

Hit-under-miss capability, allowing to serve new processor requests while a line

refill (due to a previous cache miss) is still ongoing

–

Critical-word-first refill policy, minimizing processor stalls on cache miss

–

Hit ratio improved by two-ways set-associative architecture and pLRU-t

replacement policy (pseudo-least-recently-used, based on binary tree), algorithm

with best complexity/performance balance

–

Dual master ports to decouple internal flash memory and SRAM traffic, on fast and

slow buses, respectively; also minimizing impact on interrupt latency

–

Optimal cache line refill thanks to AHB burst transactions (of the cache line size)

–

Performance monitoring by means of a hit counter and a miss counter

•

Extension of cacheable region beyond the code memory space, by means of address

remapping logic enabling the definition of four cacheable regions

•

Power consumption reduced intrinsically (more accesses to cache memory rather to

bigger main memories); even improved by configuring ICACHE as direct mapped

(rather than the default two-ways set-associative mode)

•

TrustZone security support

•

Maintenance operation for software management of cache coherency

•

Error management: detection of unexpected cacheable write access, with optional

interrupt raising

3.3

Memory protection unit

The MPU is used to manage the CPU accesses to the memory and to prevent one task to

accidentally corrupt the memory or the resources used by any other active task. This

memory area is organized into up to 16 protected areas. The MPU regions and registers are

banked across secure and nonsecure states.

The MPU is especially helpful for applications where some critical or certified code must be

protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-

time operating system).

If a program accesses a memory location prohibited by the MPU, the RTOS can detect it

and take action. In an RTOS environment, the kernel can dynamically update the MPU area

setting based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.4

Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all the masters (CPU, GPDMA1, USB OTG)

and the slaves (flash memory, SRAMs, AHB, and APB) peripherals. It also ensures a

seamless and efficient operation even when several peripherals work simultaneously.

STM32WBA62CG Datasheet(PDF) 18 Page - STMicroelectronics

STM32WBA62CG Datasheet(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL