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STM32WBA62CG Datasheet(PDF) 61 Page - STMicroelectronics |
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STM32WBA62CG Datasheet(HTML) 61 Page - STMicroelectronics |
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61 / 185 page  DS14736 Rev 1 61/185 STM32WBA6xxx Functional overview 69 3.31 Inter-integrated circuit interface (I2C) The device embeds up to four I2C, refer to Table 18 for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • I2C-bus specification and user manual rev. 5 compatibility: – Controller and target modes, multicontroller capability – Standard-mode (Sm), with a bit rate up to 100 Kbit/s – Fast-mode (Fm), with a bit rate up to 400 Kbit/s – Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os – 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses – Programmable setup and hold times – Optional clock stretching • System management bus (SMBus) specification rev 3.0 compatibility: – Hardware packet error checking (PEC) generation and verification with ACK control – Address resolution protocol (ARP) support – SMBus alert • Power system management protocol (PMBus) specification rev 1.3 compatibility • Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming • Autonomous functionality in Stop modes with wake-up from Stop capability • Programmable analog and digital noise filters • 1-byte buffer with DMA capability Table 18. I2C implementation I2C features(1) 1. X: supported I2C1 I2C2 I2C3 I2C4 Standard-mode (up to 100 Kbit/s) X X X X Fast-mode (up to 400 Kbit/s) X X X X Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X Programmable analog and digital noise filters X X X X SMBus/PMBus hardware support X X X X Independent clock X X X X Autonomous in Stop 0, 1 modes with wake-up capability X X X X Wake-up capability in Stop 2 mode - - X - |
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