STM32WBA62CG datasheet(65/185 Pages) STMICROELECTRONICS

65 / 185 page

DS14736 Rev 1

65/185

STM32WBA6xxx

Functional overview

•

Multiprocessor communications: wake-up from Mute mode by idle line detection or

address mark detection

•

Autonomous functionality in Stop modes with wake-up.

3.33

Serial peripheral interface (SPI)

The devices embed up to three serial peripheral interfaces (SPI) that can be used to

communicate with external devices while using the specific synchronous protocol. The SPI

protocol supports half-duplex, full-duplex and simplex synchronous, serial communication

with external devices.

The interface can be configured as master or slave and can operate in multislave or

multimaster configurations. The device configured as master provides communication clock

(SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be applied

optionally just to setup communication with concrete slave and to assure it handles the data

flow properly. The Motorola data format is used by default, but some other specific modes

are supported as well.

The SPI main features are:

•

Full-duplex synchronous transfers on three lines

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Half-duplex synchronous transfer on two lines (with bidirectional data line)

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Simplex synchronous transfers on two lines (with unidirectional data line)

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4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only

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Multimaster or multislave mode capability

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Dual-clock domain, separated clock for the peripheral kernel that can be independent

of PCLK

•

Baud rate prescaler up to kernel frequency/2 or bypass from RCC in master mode

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Protection of configuration and setting

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Hardware or software management of SS for both master and slave

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Adjustable minimum delays between data and between SS and data flow

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Configurable SS signal polarity and timing, MISO and MOSI swap capability

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Programmable clock polarity and phase

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Programmable data order with MSB-first or LSB-first shifting

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Programmable number of data within a transaction to control SS and CRC

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Dedicated transmission and reception flags with interrupt capability

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SPI Motorola and TI formats support

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Hardware CRC feature can secure communication at the end of transaction by:

–

Adding CRC value in Tx mode

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Automatic CRC error checking for Rx mode

•

Error detection with interrupt capability in case of data overrun, CRC error, data

underrun at slave, mode fault at master

•

Two 16 x or 8 x 8-bit embedded Rx and TxFIFOs with DMA capability

•

Programmable number of data in transaction

•

Configurable FIFO thresholds (data packing)

•

Configurable behavior at slave underrun condition (support of cascaded circular

buffers)

STM32WBA62CG Datasheet(PDF) 65 Page - STMicroelectronics

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