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STM32WBA62CGF6 Datasheet(PDF) 128 Page - STMicroelectronics |
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STM32WBA62CGF6 Datasheet(HTML) 128 Page - STMicroelectronics |
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128 / 185 page ![]() Electrical characteristics STM32WBA6xxx 128/185 DS14736 Rev 1 5.3.9 Wake-up time from low-power modes and voltage scaling transition times The times given in Table 56 are the latency between the event and the execution of the first user instruction (FSTEN = 1 in PWR_CR3 if not mentioned differently). The device goes in Low-power mode after the WFE (Wait For Event) instruction. APB2 TIM16 1.811 1.338 0.953 0.548 µA/MHz USART1 kernel clock domain 3.115 2.305 1.651 0.929 USART1 bus clock domain 4.639 3.420 2.526 1.390 SAI1 kernel clock domain 0.864 0.641 0.458 0.266 SAI1 bus clock domain 2.566 1.893 1.350 0.770 APB7 AHB to APB7(4) 0.704 0.493 0.371 0.197 SYSCFG 0.394 0.295 0.194 0.106 SPI3 kernel clock domain 0.553 0.404 0.285 0.161 SPI3 bus clock domain 1.799 1.334 0.948 0.531 LPUART1 kernel clock domain 2.243 1.667 1.187 0.682 LPUART1 bus clock domain 3.426 2.529 1.811 1.020 I2C3 kernel clock domain 1.777 1.331 0.939 0.533 I2C3 bus clock domain 2.482 1.856 1.314 0.749 LPTIM1 kernel clock domain 2.930 2.190 1.553 0.890 LPTIM1 bus clock domain 3.945 2.915 2.080 1.181 COMP 0.217 0.154 0.115 0.058 RTC/TAMP 1.530 1.145 0.821 0.453 VREFBUF 0.097 0.079 0.067 0.027 1. Evaluated by characterization, not tested in production, unless otherwise specified. 2. The AHB bus is automatically active when at least one peripheral is ON on the AHB or associated APB. 3. RADIO inactive. 4. The AHB to APB bridge is automatically active when at least one peripheral is ON on the APB. Table 55. Peripheral typical dynamic current consumption(1) (continued) Bus Peripheral Range 1 LDO Range 2 LDO Range 1 SMPS Range 2 SMPS Unit |
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