LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
17 of 70
NXP Semiconductors
LPC1766
Fast communication chip
7.7 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.7.1 Features
• Controls system exceptions and peripheral interrupts
• In the LPC1766, the NVIC supports 33 vectored interrupts
• 32 programmable interrupt priority levels, with hardware priority level masking
• Relocatable vector table
• Non-Maskable Interrupt (NMI)
• Software interrupt generation
7.7.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any pin on PORT0 and PORT2 (total of 42 pins) regardless of the selected function, can
be programmed to generate an interrupt on a rising edge, a falling edge, or both.
7.8 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or
no resistor enabled.
7.9 General purpose DMA controller
The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC1766
peripherals to have DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. The source and
destination areas can each be either a memory region or a peripheral, and can be
accessed through the AHB master. The GPDMA controller allows data transfers between
the USB and Ethernet controllers and the various on-chip SRAM areas. The supported
APB peripherals are SSP0/1, all UARTs, the I2S interface, the ADC, and the DAC. Two
match signals for each timer can be used to trigger DMA transfers.
7.9.1 Features
• Eight DMA channels. Each channel can support an unidirectional transfer.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
