
LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
36 of 70
NXP Semiconductors
LPC1766
Fast communication chip
7.30.4 APB interface
The APB peripherals are split into two separate APB buses in order to distribute the bus
bandwidth and thereby reducing stalls caused by contention between the CPU and the
GPDMA controller.
7.30.5 AHB multilayer matrix
The LPC1766 uses an AHB multilayer matrix. This matrix connects the instruction (I-code)
and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main
(32KB) static RAM, and the Boot ROM. The GPDMA can also access all of these
memories as can the peripheral DMA controllers (Ethernet and USB). Additionally, the
matrix connects the CPU system bus and all of the DMA controllers to the various
peripheral functions.
7.30.6 External interrupt inputs
The LPC1766 includes up to 46 edge sensitive interrupt inputs combined with up to four
level sensitive external interrupt inputs as selectable pin functions. The external interrupt
inputs can optionally be used to wake up the processor from Power-down mode.
7.30.7 Memory mapping control
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address
space. The vector table must be located on a 128 word (512 byte) boundary because the
NVIC on the LPC1766 is configured for 128 total interrupts.
7.31 Emulation and debugging
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four
watch points.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.