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LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
51 of 70
NXP Semiconductors
LPC1766
Fast communication chip
11.7 USB interface
[1]
Characterized but not implemented as production test. Guaranteed by design.
Table 15.
Dynamic characteristics: USB pins (full-speed)
CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3), unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
10 % to 90 %
8.5
-
13.8
ns
tf
fall time
10 % to 90 %
7.7
-
13.7
ns
tFRFM
differential rise and fall time
matching
tr /tf
--
109
%
VCRS
output signal crossover voltage
1.3
-
2.0
V
tFEOPT
source SE0 interval of EOP
see Figure 19
160
-
175
ns
tFDEOP
source jitter for differential transition
to SE0 transition
see Figure 19
−2-
+5
ns
tJR1
receiver jitter to next transition
−18.5
-
+18.5
ns
tJR2
receiver jitter for paired transitions
10 % to 90 %
−9-
+9
ns
tEOPR1
EOP width at receiver
must reject as
EOP; see
Figure 19
[1] 40
--ns
tEOPR2
EOP width at receiver
must accept as
EOP; see
Figure 19
[1] 82
--ns
Fig 19. Differential data-to-EOP transition skew and EOP width
002aab561
tPERIOD
differential
data lines
crossover point
source EOP width: tFEOPT
receiver EOP width: tEOPR1, tEOPR2
crossover point
extended
differential data to
SE0/EOP skew
n
× tPERIOD + tFDEOP
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