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LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
34 of 70
NXP Semiconductors
LPC1766
Fast communication chip
Depending on the LPC1766 application, a design can use two power options to manage
power consumption.
The first option assumes that power consumption is not a concern and the design ties the
VDD(3V3) and VREG(3V3) pins together. This approach requires only one 3.3 V power supply
for both pads, the CPU, and peripherals. While this solution is simple, it does not support
powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and
a dedicated 3.3 V supply for the CPU (VREG(3V3)). Having the on-chip voltage regulator
powered independently from the I/O pad ring enables shutting down of the I/O pad power
supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. Whenever the device core
power (VREG(3V3)) is present, that power is used to operate the RTC. Therefore, there is
no power drain from the RTC battery when VREG(3V3) is available.
Fig 5.
Power distribution
REAL-TIME CLOCK
BACKUP REGISTERS
3.3 V REGULATOR
32 kHz
OSCILLATOR
POWER
SELECTOR
ULTRA-LOW
POWER
REGULATOR
RTC POWER DOMAIN
MAIN POWER DOMAIN
002aad978
RTCX1
VBAT
VREG(3V3)
RTCX2
VDD(3V3)
VSS
to memories,
peripherals,
oscillators,
PLLs
to core
to I/O pads
ADC
DAC
ADC POWER DOMAIN
VDDA
VREFP
VREFN
VSSA
LPC17xx
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