LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
20 of 70
NXP Semiconductors
LPC1766
Fast communication chip
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
• Physical interface:
– Attachment of external PHY chip through standard RMII interface.
– PHY register access is available via the MIIM interface.
7.12 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC1766 USB interface includes a device, Host, and OTG controller with on-chip
PHY for device and Host functions. The OTG switching protocol is supported through the
use of an external controller. Details on typical USB interfacing solutions can be found in
Section 14.1.
7.12.1 USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the on-chip
SRAM (see Figure 1).
7.12.1.1
Features
• Fully compliant with USB 2.0 specification (full speed).
• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
• Supports SoftConnect and GoodLink features.
• While USB is in the Suspend mode, the LPC1766 can enter one of the reduced power
modes and wake up on USB activity.
• Supports DMA transfers with the on-chip SRAM blocks of 32 kB and 2 kB on all
non-control endpoints.
• Allows dynamic switching between CPU-controlled slave and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
