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LPC1766_0.02
© NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 — 12 August 2008
53 of 70
NXP Semiconductors
LPC1766
Fast communication chip
Fig 21.
SPI master timing (CPHA = 0)
SCK (CPOL = 0)
MOSI
MISO
002aad987
tSPICLK
tSPICLKH
tSPICLKL
tSPIDSU
tSPIDH
DATA VALID
DATA VALID
tSPIOH
SCK (CPOL = 1)
DATA VALID
DATA VALID
tSPISEDV
Fig 22.
SPI slave timing (CPHA = 1)
SCK (CPOL = 0)
MOSI
MISO
002aad988
tSPICLK
tSPICLKH
tSPICLKL
tSPIDSU
tSPIDH
tSPISEDV
DATA VALID
DATA VALID
tSPIOH
SCK (CPOL = 1)
DATA VALID
DATA VALID