HD6417618A datasheet(518/646 Pages) RENESAS

518 / 646 page

Section 18 User Break Controller (UBC)

Rev. 6.00 Jun. 12, 2007 Page 486 of 610

REJ09B0131-0600

This means that when address H'00001003 is set in the break address register (BARA or

BARB), for example, the bus cycle in which the break condition is satisfied is as follows

(where other conditions are met).

 Longword access at H'00001000

 Word access at H'00001002

 Byte access at H'00001003

• When the data value is included in the break conditions on channel B:

When the data value is included in the break conditions, either longword, word, or byte is

specified as the operand size of the break bus cycle registers (BBRA and BBRB). In this case,

a break is generated when the address conditions and data conditions both match. To specify

byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break

data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set,

bits 31 to 16 of BDRB and BDMRB are ignored.

18.3.4

Sequential Break

• By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break

condition matches after a channel A break condition matches. A user break is not generated

even if a channel B break condition matches before a channel A break condition matches.

When channels A and B break conditions match at the same time, the sequential break is not

issued. To clear the channel A condition match when a channel A condition match has

occurred but a channel B condition match has not yet occurred in a sequential break

specification, clear the SEQ bit in BRCR to 0.

• In sequential break specification, the L- or I-bus can be selected and the execution times break

condition can be also specified. For example, when the execution times break condition is

specified, the break is generated when a channel B condition matches with BETR = H'0001

after a channel A condition has matched.

18.3.5

Value of Saved Program Counter (PC)

When a break occurs, PC is saved onto the stack. The PC value saved is as follows depending on

the type of break.

• When a break before execution is selected:

The value of the program counter (PC) saved is the address of the instruction that matches the

break condition. The fetched instruction is not executed, and a break occurs before it.

HD6417618A Datasheet(PDF) 518 Page - Renesas Technology Corp