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R5F2L3ACBNFP Datasheet(PDF) 153 Page - Renesas Technology Corp |
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R5F2L3ACBNFP Datasheet(HTML) 153 Page - Renesas Technology Corp |
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153 / 848 page  7. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 117 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Notes: 1. Pulled up by setting the corresponding bit in the P11PUR register to 1. 2. Output drive capacity high by setting the corresponding bit in the P10DRR register to 1. 3. N-channel open-drain output by setting the SCKOS bit in the SSMR2 register to 1. 4. N-channel open-drain output by setting the NODC bit in the U2SMR3 register to 1. 5. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output) and setting the BIDE bit to 0 (standard mode). 6. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1. 7. Synchronous serial communication unit (refer to Table 27.4 Association between Communication Modes and I/O Pins). Table 7.18 Ports P11_0 and P11_1 Pin Register PD11 INTSR INTEN INTCMP ACMR SSUIICSR ICCR1 SSU Associated Register (7) U2SR1 U2MR Function Bit PD11_i INTi SEL0 INTiEN INT1 CP0 CM10E IICSEL ICE SSCK output control SSCK input control CLK2SEL0 SMD CKDIR 21 0 Port P11_0 SCL SSCK (CLK2 INT0) IVREF1 LVCOUT1 i = 0 0X X X 0 0X 0 0 0X X X X Input port (1) 10 X X 1X X X 0 0X 0 0 0X X X X Output port (2) 10 X X 0X X X 0 1 1 X X 0 X X X X SCL input/output (2) 0X X X 0 0 X 0 1 0 X X X X SSCK input (1) 0X X X 0 0 X 1 0 0 X X X X SSCK output (2, 5) 0X X X 0 0X 0 0 1X X X 1 CLK2 input (1) 10 X X 0X X X 0 0X 0 0 1 001 0 CLK2 output (2, 6) 10 X X 01 1 X 0 0X 0 0 0X X X X INT0 input (1) 10 X X 0X X 1 0 0X 0 0 0X X X X Comparator B1 reference voltage input (IVREF1) 10 X X XX X X 1 0X 0 0 0X X X X Comparator A1 output (LVCOUT1) (2) 10 X X Pin Register PD11 INTSR INTEN INTCMP ACMR SSUIICSR SSU Associated Register (7) U2SR0 U2MR U2SMR Function Bit PD11_i INTi SEL0 INTiEN INT1 CP0 CM20E IICSEL SSI output control SSI input control RXD2 SEL TXD2 SEL SMD IICM 10 10 2 1 0 Port P11_1 SSI (RXD2 SCL2 TXD2 SDA2 INT1) IVCMP1 LVCOUT2 i = 1 0X X X 0 X 0 0 X X Other than 10b XX X X Input port (1) 1X X X 0 X 0 0 X X X X X X Output port (2) 0X X X 0 0 0 1 X X X X X X SSI input (1) XX X X 0 0 1 0 X X X X X X SSI output (2, 5) 0X X X 0 X 0 0 0 1 X X X 0 RXD2 input (1) 0 X X X 0 X 0 0 0 1 010 1 SCL2 input/output (2, 6) XX X X 0 X 0 0 X X 1 0 001 0 TXD2 output (2, 6) 10 X 0 110 0 0 X X X 0 X 0 0 X X 1 0 010 1 SDA2 input/output (2, 6) 0 1 100 X 0 0 X X Other than 10b XX X X INT1 input (1) 0 0 110 X 0 0 X X X X X X Comparator B1 input (IVCMP1) 0X X X 1 X 0 0 X X X X X X Comparator A2 output (LVCOUT2) (2) |
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