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R5F2L3ACBNFP Datasheet(PDF) 157 Page - Renesas Technology Corp |
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R5F2L3ACBNFP Datasheet(HTML) 157 Page - Renesas Technology Corp |
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157 / 848 page  7. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 121 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Notes: 1. Pulled up by setting the corresponding bit in the P13PUR register to 1. 2. N-channel open-drain output by setting the NCH bit in the U0C0 register to 1. Table 7.22 Ports P13_0 to P13_3 Pin Register PD13 ADINSEL DACON — Function Bit PD13_i CH ADGSEL DA0E 21 0 1 0 Port P13_0 AN0 DA0 WKUP1 i = 0 0X X X X X 0 Input port (1) 1 X X X X X 0 Output port 0X X X X X 0 WKUP1 input (1) 00 0 0 0 0 0 A/D converter input (AN0) (1) 0X X X X X 1 D/A converter output (DA0) Pin Register PD13 ADINSEL DACON VCA2 U0SR U0MR — Function Bit PD13_i CH ADGSEL DA1E VCA21 VCA23 TXD0 SEL0 SMD 21 0 1 0 2 1 0 Port P13_1 AN1 DA1 TXD0 LVREF i = 1 0X X X X X 0 X X 0 X X X Input port (1) 1 X X X X X 0 X X 0 X X X Output port 00 0 1 0 0 0 X X 0 X X X A/D converter input (AN1) (1) 0X X X X X 1 X X 0 X X X D/A converter output (DA1) 0X X X X X 0 X X 1 00 1 TXD0 output (2) 10 X 11 0 0X X X X X 0 1 X 0 X X X Comparator A1 reference input (LVREF) 0X X X X X 0 X 1 0 X X X Comparator A2 reference input (LVREF) Pin Register PD13 ADINSEL — VCA2 U0SR — Function Bit PD13_i CH ADGSEL —VCA22 RXD0 SEL 21 0 1 0 1 0 Port P13_2 AN2 RXD0 LVCMP1 i = 2 0X X X X X — X X X Input port (1) 1 X X X X X — X X X Output port 00 1 0 0 0 — X X X A/D converter input (AN2) (1) 0X X X X X — X 0 1 RXD0 input (1) 0X X X X X — 1 X X Comparator A1 input (LVCMP1) Pin Register PD13 ADINSEL — VCA2 U0SR U0MR — Function Bit PD13_i CH ADGSEL — VCA24 CLK0 SEL0 SMD CKDIR 2 1 0 1 0 210 Port P13_3 AN3 CLK0 LVCMP2 i = 3 0X X X X X — X 0X X X X Input port (1) 1 X X X X X — X 0 X X X X Output port 0 0 1 1 0 0 — X 0 XXX X A/D converter input (AN3) (1) 0X X X X X — X 1X X X 1 CLK0 (external clock input) (1) X X X X X X — X 1 001 0 CLK0 (internal clock) output 0X X X X X — 1 0X X X X Comparator A2 input (LVCMP2) |
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