R5F2L3ACBNFP datasheet(160/848 Pages) RENESAS

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8. Bus

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 124 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

Bus

The bus cycles differ when accessing ROM/RAM and when accessing SFR.

Table 8.1 lists the Bus Cycles by Access Area.

ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are

accessed twice in 8-bit units.

Table 8.2 shows Access Units and Bus Operations.

Note:

1. Data flash is provided only in the following four: the R8C/L35A Group, L36A Group, L38A Group,

and L3AA Group.

Table 8.2

Access Units and Bus Operations

Table 8.1

Bus Cycles by Access Area

Access Area

Bus Cycle

SFR/Data flash

2 cycles of CPU clock

Program ROM/RAM

1 cycle of CPU clock

Area

SFR, Data flash

Even address

Byte access

ROM (program ROM), RAM

Odd address

Byte access

Even address

Word access

Odd address

Word access

CPU clock

Data

Even

Address

CPU clock

Data

Address

CPU clock

Data

Address

CPU clock

Data

Address

CPU clock

Data

Address

CPU clock

Data

Address

CPU clock

Data

Address

CPU clock

Data

Address

Data

Odd

Data

Even

Even + 1

Data

Odd

Odd + 1

Data

Even

Even + 1

Data

Odd

Odd + 1

Data

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