R5F2L3ACBNFP datasheet(196/848 Pages) RENESAS

196 / 848 page

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 160 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

10. Power Control

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

10.5.3

Exiting Stop Mode

The MCU exits stop mode by a reset or peripheral function interrupt.

Figure 10.4 shows the Time from Stop Mode to Interrupt Routine Execution.

To use a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1.

(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for

exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for

exiting stop mode to 000b (interrupt disabled).

(2) Set the I flag to 1.

(3) Operate the peripheral function to be used for exiting stop mode.

When the MCU exits stop mode by a peripheral function interrupt, the interrupt sequence is executed when

an interrupt request is generated and the CPU clock supply starts.

The clock used immediately before stop mode divided by 8 is used as the CPU clock when the MCU exits stop

mode by a peripheral function interrupt. To enter stop mode, set the CM35 bit in the CM3 register to 0 (settings

of CM06 bit in CM0 register and bits CM16 and CM17 in CM1 register enabled).

Figure 10.4

Time from Stop Mode to Interrupt Routine Execution

Interrupt request generation

100

µs (max.)

Stop mode

Internal power

stabilization time

Oscillation time of CPU clock

source used immediately

before stop mode

Interrupt sequence

Flash memory

activation sequence

CPU clock

restart sequence

100

µs (max.)

Internal Power

Stabilization Time (T0)

100

µs (max.)

Period of system clock

× 1 cycle + 60 µs (max.)

Period of system clock

× 1 cycle

Period of CPU clock

× 2 cycles

Same as above

Time until

CPU Clock

Supply (T3)

Time until

Flash Memory

Activation (T2)

Time for

Interrupt

Sequence (T4)

Period of CPU clock

× 20 cycles

Same as above

FMSTP Bit

(flash memory operates)

(flash memory stops)

FMR0 Register

The total of T0 to T4 is

the time from wait mode

until an interrupt routine

is executed.

Remarks

R5F2L3ACBNFP Datasheet(PDF) 196 Page - Renesas Technology Corp

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