SH7713 datasheet(47/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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47 / 904 page

Section 1 Overview and Pin Function

Rev.1.50 Aug. 30, 2006 Page 7 of 860

REJ09B0288-0150

1.2

Block Diagram

SuperH

CPU core

X/Y memory

Instructions/data for

CPU/DSP 16 kbytes

User break

controller

(UBC)

DSP core

Cache

access

controller

(CCN)

Direct

memory

access

controller

(DMAC)

Memory

management

unit

(MMU)

Cache

memory

32 kbytes

Bus state

controller

(BSC)

Peripheral

bus

controller

Ethernet

controller

direct memory

access

controller

(E-DMAC)

CPU bus (I clock)

Internal bus (B clock)

External bus

Note: * SCIF and SIOF have two channels respectively.

128-byte

SRAM

Serial I/O

with FIFO

(SIOF)*

User

debugging

interface

(H-UDI)

Interrupt

controller

(INTC)

Realtime

clock

(RTC)

Timer

unit

(TMU)

On-chip

oscillation

circuits

(CPG)

(WDT)

Serial

communication

interface

with FIFO

(SCIF)*

Transmit FIFO

(2 kbytes)

Ethernet controller

(EtherC)

Receive FIFO

(2 kbytes)

X bus

Y bus

Ethernet

Peripheral bus (P clock)

Advanced

user

debugger

(AUD)

L bus

Figure 1.1 Block Diagram

SH7713 Datasheet(PDF) 47 Page - Renesas Technology Corp

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