SH7713 datasheet(88/904 Pages) RENESAS

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Section 2 CPU

Rev.1.50 Aug. 30, 2006 Page 48 of 860

REJ09B0288-0150

Addressing

Mode

Instruction

Format

Effective Address Calculation Method

Calculation

Formula

PC-relative

Effective address is sum of PC and Rn.

PC + Rn

#imm:8

8-bit immediate data imm of TST, AND,

OR, or XOR instruction is zero-extended.

—

#imm:8

8-bit immediate data imm of MOV, ADD, or

CMP/EQ instruction is sign-extended.

—

Immediate

#imm:8

8-bit immediate data imm of TRAPA

instruction is zero-extended and multiplied

by 4.

—

Note:

For addressing modes with displacement (disp) as shown below, the assembler description

in this manual indicates the value before it is scaled (x 1, x2, or x4) according to the

operand size to clarify the LSI operation. For details on assembler description, refer to the

description rules in each assembler.

@ (disp:4, Rn) ; Register indirect with displacement

@ (disp:8, GBR)

; GBR indirect with displacement

@ (disp:8, PC) ; PC relative with displacement

disp:8, disp

; PC relative

2.5.3

CPU Instruction Formats

Table 2.4 shows the instruction formats, and the meaning of the source and destination operands,

for instructions executed by the CPU core. The meaning of the operands depends on the

instruction code. The following symbols are used in the table.

xxxx: Instruction code

mmmm:

Source register

nnnn: Destination register

iiii:

Immediate data

dddd: Displacement

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