SH7713 datasheet(167/904 Pages) RENESAS

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Section 3 DSP Operating Unit

Rev.1.50 Aug. 30, 2006 Page 127 of 860

REJ09B0288-0150

Source 1

1 0

MAC

Ignored

Source 2

Destination

Figure 3.16 Fixed-Point Multiply Operation Flow

Table 3.25

Variation of Fixed-Point Multiply Operation

Mnemonic

Function

Source 1

Source 2

Destination

PMULS

Signed multiplication

Table 3.26

Correspondence between Operands and Registers

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Yes

—

Note:

The multiply operations basically generate 32-bit operation results. So when a register

providing the guard-bit parts are specified as a destination operand, the guard-bit parts will

copy bit 31 of the operation result.

The multiply operation of the DSP unit side is not integer but fixed-point arithmetic. So, the upper

words of each multiplier and multiplicand are input into a MAC unit as shown in figure 3.16. In

the SH's standard multiply operations, the lower words of both source operands are input into a

MAC unit. The operation result is also different from the SH's case. The SH's multiply operation

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