AT90SCR100 datasheet(176/433 Pages) ATMEL

176 / 433 page

176

TPR0327AY–SMS–30Jan09

AT90SCR100

visor RAM Illegal Access Attempt Violation security interrupt (if not masked) is so triggered.

USBDMADH, USBDMADL and USBDMAB registers keep their previous value.

14.9.3

USBDMAB - USBDMA Amount of Bytes Register

This register is dedicated to the amount of bytes to be transferred during the next USBDMA

operation setting.

• Bit 7 - Res : Reserved Bit

This bit is reserved bit in the AT90SCR100 and is always read as zero.

• Bits 6..0 - USBDMAB6..0 : DMA Amount of Bytes Bits

These bits are the (6..0) bits of the 7-bit USBDMA Amount of Bytes value.

When starting a USBDMA operation, the hardware will check if the values of USBDMADH, USB-

DMADL and USBDMAB registers does not exceed the specific RAM area ($000100 to

$0010FF). If an error is detected, USBDMACS.DMAERR bit is automatically set (one). A Super-

visor RAM Illegal Access Attempt Violation security interrupt (if not masked) is so triggered.

USBDMADH, USBDMADL and USBDMAB registers keep their previous value.

After a USBDMA operation, USBDMADH and USBDMADL are set to the last

value reached in RAM and incremented by one. For instance, after a 64-byte

transfer started from base address $000100, USBDMAD equals to $000140 (USB-

DMADH = $01 and USBDMADL = $40). This feature allows to simplify registers

and bits handlings when several USBDMA operations are to be successively per-

formed, which can be the case when getting or sending several packets.

Note

Bit

6543

$0000ED

USBDMAB [6..0]

USBDMAB

Read/write

R/W

Initial value

0x00

After a USBDMA operation completion, the value of this register is not reset.

The maximum value allowed for USBDMAB depends on the endpoint selected.

Note

AT90SCR100 Datasheet(PDF) 176 Page - ATMEL Corporation