AT90SCR100 datasheet(172/433 Pages) ATMEL

172 / 433 page

172

TPR0327AY–SMS–30Jan09

AT90SCR100

The software must update these bits with the address value received during a valid

SET_ADDRESS request.

It must then set (one) the bit USBGS.FAF (see “USBGS - USB Global State Register” on page

171).

14.8.13

USBFN - USB Frame Number Registers

• Bits 15..13 - Res: Reserved Bits

These bits are reserved bits in the AT90SCR100 and are always read as zero.

• Bit 12 - FNEND : Frame Number End Bit

This bit is set (one) and cleared (zero) by hardware.

This bit is set (one) when an End Of Packet Start Of Frame (SOF) transaction has occurred.

This bit is cleared (zero) by the next detected SOF.

• Bit 11 - FNERR : Frame Number Error Bit

This bit is set (one) and cleared (zero) by hardware.

This bit is set (one) if the last Frame Number Field received is corrupted. Otherwise it is cleared

(zero).

• Bits 10..0 - FN10..0 : Frame Number Bits

These bits are set (one) and cleared (zero) by hardware.

These bits represent the Frame Number value.

14.9

USBDMA Controller

The USBDMA controller, implemented on the AT90SCR100, is intended to be used for execut-

ing fast transfers between the RAM memory and the DPRAM (Dual Port RAM) which is

dedicated to the USB endpoints. This feature allows the application software of the

AT90SCR100 to manage the exchanges imposed by the USB protocol.

Bit

141312

$0000E9

FNEND

FNERR

FN10

FN9

FN8

USBFNH

$0000E8

FN7

FN6

FN5

FN4

FN3

FN2

FN1

FN0

USBFNL

Bit

7654

Read/write

RRRRR

Initial value

0000

0x00

0000

0x00

The Frame Number value represented by the eleven bits USBFNH.FN2..0 and

USBFNL.FN7..0 should only be read when bit USBFNH.FNEND is set (one).

Note

All the USB registers described in this section cannot be accessed if the USB

module is not enabled.

Caution

AT90SCR100 Datasheet(PDF) 172 Page - ATMEL Corporation

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