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AT90SCR100 Datasheet(PDF) 169 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 169 Page - ATMEL Corporation |
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169 / 433 page ![]() 169 TPR0327AY–SMS–30Jan09 AT90SCR100 • Bit 1 - RCVD : Received Data Bit This bit is a status bit. It is set (one) by hardware and cleared (zero) by software. If it is set (one), the DPRAM of the corresponding endpoint is filled with data coming from the host through the USB bus. This bit is a source for the Endpoint interrupt and must be cleared to acknowledge the interruption. • Bit 0 - TXC : Tx Complete Bit This bit is a status bit. It is set (one) by hardware and cleared (zero) by software. If it is set (one), an ACK handshake from the host has been received on the corresponding end- point through the USB bus. This bit is a source for the Endpoint interrupt and must be cleared to acknowledge the interruption. 14.8.8 USBDBCEX - USB Data Byte Count Registers for Endpoint X Set USBENUM register to point to the relevant Endpoint before using the USBDBCEX register. If a packet of data has been received from the host in the corresponding endpoint through the USB bus, these registers indicate the amount of data bytes available in the DPRAM. The value is considered valid if the bit USBCSEX.RCVD has been previously set by hardware. • Bits 7..0 - BCT7..0 : Bytes Count Bits These bits are set (one) and cleared (zero) by hardware. 14.8.9 USBFCEX - USB Function Control Registers for Endpoint X Set USBENUM register to point to the relevant Endpoint before using the USBFCEX register. • Bits 7 - EPE : Endpoint Enable Bit This bit is set (one) and cleared (zero) by software. When it is set (one) the corresponding endpoint is enabled. When it is cleared (zero) the corresponding endpoint is disabled. A disabled endpoint does not respond when addressed (read or written) by the host. Bit 76543 2 1 0 $0000CC BCT7 BCT6 BCT5 BCT4 BCT3 BCT2 BCT1 BCT0 USBDBCEX Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000 0 0 0 0x00 Bit 7654 3 2 1 0 $0000CD EPE ---- EPDIR EPTYP1 EPTYP0 USBFCEX Read/write R/W RRRR R/W R/W R/W Initial value 0000 0 0 0 0 0x00 |
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