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AT90SCR100 Datasheet(PDF) 167 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 167 Page - ATMEL Corporation |
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167 / 433 page ![]() 167 TPR0327AY–SMS–30Jan09 AT90SCR100 This bit is cleared (zero) by hardware when the endpoint interrupt source has been cleared (zero) by the software (see “USBCSEX - USB Control And Status Register for Endpoint X” on page 167). 14.8.5 USBEIM - USB Endpoint Interrupt Mask Register See “USBEI - USB Endpoint Interrupt Register” on page 166. • Bit n - EPnIM : Endpoint n Interrupt Mask Bit (n=0..7) When EPnIM is set (one) the Endpoint n interrupt is enabled. When EPnIM is cleared (zero) the Endpoint n interrupt is masked. 14.8.6 USBENUM - USB Endpoint Number Register • Bit 7..3 - Res : Reserved Bits These bits are reserved and are always read as zero. • Bit 2..0 - ENUM2..0 : Endpoint Number Use this register to select an endpoint. The USB Device registers ended by a X correspond then to this number. 14.8.7 USBCSEX - USB Control And Status Register for Endpoint X Set USBENUM register to point to the relevant Endpoint before using the USBCEX register. The endpoint interrupt conditions are listed below and further detailed in “USBC- SEX - USB Control And Status Register for Endpoint X” on page 167. They are the same for the seven endpoints ( 0 ≤ n ≤ 7): • USBCSEn.TXC bit is set in Bulk In, Interrupt In or Control mode. • USBCSEn.RCVD bit is set in Bulk Out, Interrupt Out, Isochronous Out or Control mode. • USBCSEn.RXSETUP is set in Control mode. • USBCSEn.STSENT bit is set in Bulk, Interrupt or Control mode. Note Bit 7654 3 2 1 0 $0000E5 EP7IM EP6IM EP5IM EP4IM EP3IM EP2IM EP1IM EP0IM USBEIM Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0000 0 0 0 0 0x00 Bit 7 6543 2 1 0 $0000CA ----- ENUM [2..0] USBENUM Read/write R R R R R R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x00 Bit 7654 3 2 1 0 $0000CB - IERR FSTALL TXPB STSENT RXSETUP RCVD TXC USBCSEX Read/write R R R/W R/W R/W R/W R/W R/W Initial value 0000 0 0 0 0 0x00 |
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