AT90SCR100 datasheet(165/433 Pages) ATMEL

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AT90SCR100

• Bit 1 - USBE : USB Enable Bit

You must clear this bit before using it, even if the USB module has not been used previously.

Set this bit to enable the USB controller.

Clear this bit to disable and reset the USB controller, to disable the USB transceiver and to dis-

able the USB controller clock inputs.

• Bit 0 - Res : Reserved Bit

This bit is reserved and will always be read as zero.

14.8.2

USBPI - USB Protocol Interrupt register

The following interrupt sources are all sources for the USB Protocol interruption

• Bits 7..5 - Res : Reserved Bits

These bits are reserved bits in the AT90SCR100 and are always read as zero.

• Bit 4 - FEURI : Falling Edge on USB Reset Interrupt Bit

Set (one) by hardware when a falling edge on the USB Reset has occurred. This bit indicates

the end of the USB bus Reset signaling.

This interruption is not maskable at the USBPIM register level (see “USBPIM - USB Protocol

Interrupt Mask Register” on page 166).

Cleared (zero) by software.

• Bit 3 - SOFI : Start Of Frame Interrupt Bit

Set (one) by hardware when a Start Of Frame PID has been detected on the USB bus.

Cleared (zero) by software.

• Bit 2 - RMWUI :Remote WakeUp Interrupt Bit

Set (one) byt hardware when the USBCR.URMWU bit is set.

Cleared (zero) by software.

• Bit 1 - RESI : Resume Interrupt Bit

Set (one) by hardware when a USB Resume signal has been detected on the USB bus.

Cleared (zero) by software.

• Bit 0 - SUSI : Suspend Interrupt Bit

Set (one) by hardware when a USB Suspend signal has been detected on the USB bus.

Clearing the USBE bit will freeze the USB macro the same way as PRR1.PRUSB.

Anyway, these two bits are independant, and for the USB macro to run, USBE

must be set and PRUSB must be cleared. See “PRR1 – Power Reduction Register

1” on page 46.

Note

Bit

7654

$0000E1

FEURI

SOFI

RMWUI

RESI

SUSI

USBPI

Read/write

R/W

Initial value

0000

0x00

AT90SCR100 Datasheet(PDF) 165 Page - ATMEL Corporation

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