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AT90SCR100 Datasheet(PDF) 174 Page - ATMEL Corporation

Part # AT90SCR100
Description  8-bit Microcontroller for Smart Card Readers
PDF  433 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT90SCR100 Datasheet(HTML) 174 Page - ATMEL Corporation

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174
TPR0327AY–SMS–30Jan09
AT90SCR100
These bits are set (one) and cleared (zero) by software.
They are used to select the source or destination endpoint for the next USBDMA operation.
• Bit 3 - Res : Reserved Bit
This bit is reserved in the AT90SCR100 and is always read as zero.
• Bit 2 - USBDMAERR : USB DMA Error Bit
When launching the USBDMA controller, this bit is cleared (zero) by the hardware if the values
into USBDMADH, USBDMADL and USBDMAB registers are suitable for the USBDMA operation
requested.
This bit can also be cleared(zero) by software.
This bit is set (one) by hardware when starting a USBDMA operation and whenever one of these
following cases occurs:
• The base address contained in the registers USBDMADH and USBDMADL is incorrect (out
of the allowed range).
• According to the values of the registers USBDMADH, USBDMADL and USBDMAB and even
if the base address is correct, an address out of the allowed range is going to be reached.
• The value in the register USBDMAB is greater than the size of the selected endpoint for the
USBDMA operation (see bits USBDMACS.EPS2:0 below).
When this bit is set, and if the USB unterruptions are enabled, a USB interruption is generated.
• Bit 1 - USBDMADIR : USB DMA Direction Bit
This bit is set (one) and cleared (zero) by software.
It indicates the direction of the next USBDMA operation transfer between the RAM memory and
the selected endpoint (represented by the bits USBDMACS.EPS2:0):
A violation is triggered if a USBDMA operation is launched with 0 byte to transfer
or when USBMACS.EPS2:0 value is more than 4.
Table 14-2.
Endpoint Selection Bits
EPS2
EPS1
EPS0
Endpoint Selected
Endpoint Size (Bytes)
0
0
0
Endpoint 0
64
0
0
1
Endpoint 1
2x64
0
1
0
Endpoint 2
2x64
0
1
1
Endpoint 3
64
1
0
0
Endpoint 4
8
1
0
1
Endpoint 5
8
1
1
0
Endpoint 6
8
1
1
1
Endpoint 7
8
Don’t forget to clear the USBDMACS.DMAERR bit before leaving the interruption
routine to avoid repetitive and endless interruptions.
Note
Caution
!



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