SPMCK16Z4MPV20 datasheet(258/500 Pages) FREESCALE

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MULTICHANNEL COMMUNICATION INTERFACE

M68HC16 Z SERIES

10-18

USER’S MANUAL

10.4.5.2 Serial Formats

All data frames must have a start bit and at least one stop bit. Receiving and transmit-

ting devices must use the same data frame format. The SCI provides hardware sup-

port for both 10-bit and 11-bit frames. The M bit in SCCR1 specifies the number of bits

per frame.

The most common data frame format for NRZ serial interfaces is one start bit, eight

data bits (LSB first), and one stop bit; a total of ten bits. The most common 11-bit data

frame contains one start bit, eight data bits, a parity or control bit, and one stop bit.

Ten-bit and eleven-bit frames are shown in Table 10-6.

10.4.5.3 Baud Clock

The SCI baud rate is programmed by writing a 13-bit value to the SCBR field in SCI

control register zero (SCCR0). The baud rate is derived from the MCU system clock

by a modulus counter. Writing a value of zero to SCBR[12:0] disables the baud rate

generator. Baud rate is calculated as follows:

where SCBR[12:0] is in the range {1, 2, 3, ..., 8191}.

The SCI receiver operates asynchronously. An internal clock is necessary to synchro-

nize with an incoming data stream. The SCI baud rate generator produces a receive

time sampling clock with a frequency 16 times that of the SCI baud rate. The SCI de-

termines the position of bit boundaries from transitions within the received waveform,

and adjusts sampling points to the proper positions within the bit period.

Table 10-6 Serial Frame Formats

10-Bit Frames

Start

Data

Parity/Control

Stop

—

1711

—

11-Bit Frames

Start

Data

Parity/Control

Stop

1712

1811

SCI Baud Rate

sys

SCBR[12:0]

--------------------------------------------

SCBR[12:0]

sys

SCI Baud Rate Desired

---------------------------------------------------------------------------

Freescale Semiconductor, Inc.

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